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gpu: nvgpu: add tsg_open HAL interface

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Add HAL interface for TSG open, which is intended to
be called from the exisiting gk20a_tsg_open function.

The tsg_open entryoint is only implemented for vgpu,
as the server needs to clear metadata when a tsg is opened.

Bug 200215060

Change-Id: Icc8fd602f31e52d9fa9b2e7786b665b9e7b9294e
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1249218
(cherry picked from commit 35c86f7c796c6574d3dc336e20012ea5c16d7cb4)
Reviewed-on: http://git-master/r/1256468
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sachit Kadle
2016-11-04 17:48:59 -07:00
committed by mobile promotions
parent 6ea4a81f4d
commit c1750f45f5
4 changed files with 44 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -392,6 +392,7 @@ struct gpu_ops {
int (*tsg_bind_channel)(struct tsg_gk20a *tsg,
struct channel_gk20a *ch);
int (*tsg_unbind_channel)(struct channel_gk20a *ch);
int (*tsg_open)(struct tsg_gk20a *tsg);
u32 (*eng_runlist_base_size)(void);
int (*init_engine_info)(struct fifo_gk20a *f);
u32 (*runlist_entry_size)(void);

14
drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
View File

@@ -402,6 +402,7 @@ int gk20a_tsg_open(struct gk20a *g, struct file *filp)
{
struct tsg_gk20a *tsg;
struct device *dev;
int err;
dev = dev_from_gk20a(g);
@@ -426,11 +427,24 @@ int gk20a_tsg_open(struct gk20a *g, struct file *filp)
filp->private_data = tsg;
if (g->ops.fifo.tsg_open) {
err = g->ops.fifo.tsg_open(tsg);
if (err) {
gk20a_err(dev, "tsg %d fifo open failed %d",
tsg->tsgid, err);
goto clean_up;
}
}
gk20a_dbg(gpu_dbg_fn, "tsg opened %d\n", tsg->tsgid);
gk20a_sched_ctrl_tsg_added(g, tsg);
return 0;
clean_up:
kref_put(&tsg->refcount, gk20a_tsg_release);
return err;
}
int gk20a_tsg_dev_open(struct inode *inode, struct file *filp)

23
drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
View File

@@ -23,6 +23,28 @@
#include "gk20a/tsg_gk20a.h"
#include "vgpu.h"
static int vgpu_tsg_open(struct tsg_gk20a *tsg)
{
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_tsg_open_params *p =
&msg.params.tsg_open;
int err;
gk20a_dbg_fn("");
msg.cmd = TEGRA_VGPU_CMD_TSG_OPEN;
msg.handle = vgpu_get_handle(tsg->g);
p->tsg_id = tsg->tsgid;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err ? err : msg.ret;
if (err) {
gk20a_err(dev_from_gk20a(tsg->g),
"vgpu_tsg_open failed, tsgid %d", tsg->tsgid);
}
return err;
}
static int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
struct channel_gk20a *ch)
{
@@ -101,4 +123,5 @@ void vgpu_init_tsg_ops(struct gpu_ops *gops)
gops->fifo.tsg_bind_channel = vgpu_tsg_bind_channel;
gops->fifo.tsg_unbind_channel = vgpu_tsg_unbind_channel;
gops->fifo.tsg_set_timeslice = vgpu_tsg_set_timeslice;
gops->fifo.tsg_open = vgpu_tsg_open;
}

6
include/linux/tegra_vgpu.h
View File

@@ -98,6 +98,7 @@ enum {
TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61,
TEGRA_VGPU_CMD_GET_CONSTANTS = 62,
TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63,
TEGRA_VGPU_CMD_TSG_OPEN = 64,
};
struct tegra_vgpu_connect_params {
@@ -387,6 +388,10 @@ struct tegra_vgpu_tsg_timeslice_params {
u32 timeslice_us;
};
struct tegra_vgpu_tsg_open_params {
u32 tsg_id;
};
/* level follows nvgpu.h definitions */
struct tegra_vgpu_tsg_runlist_interleave_params {
u32 tsg_id;
@@ -486,6 +491,7 @@ struct tegra_vgpu_cmd_msg {
struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx;
struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx;
struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel;
struct tegra_vgpu_tsg_open_params tsg_open;
struct tegra_vgpu_tsg_preempt_params tsg_preempt;
struct tegra_vgpu_tsg_timeslice_params tsg_timeslice;
struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave;