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gpu: nvgpu: nvgpu_memcpy changes to pmgr code

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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.

To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.

This change switches non-offending memcpy usage in pmgr/* code
over to to use nvgpu_memcpy() with appropriate casts applied
to maintain consistency within nvgpu.

JIRA NVGPU-849

Change-Id: If4c9b1042e1974ae025ca6d4874a16b7e12e74c9
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Scott Long
2018-11-08 20:19:52 -08:00
committed by mobile promotions
parent f1747cbcd1
commit c1cdb9d363
2 changed files with 10 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/pmgr/pmgrpmu.c
View File

@@ -26,6 +26,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/string.h>
#include "gp106/bios_gp106.h"
@@ -329,12 +330,12 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g)
ppwrpack->policies.hdr.data.low_sampling_mult =
g->pmgr_pmu.pmgr_policyobjs.low_sampling_mult;
(void) memcpy(&ppwrpack->policies.hdr.data.global_ceiling,
&g->pmgr_pmu.pmgr_policyobjs.global_ceiling,
nvgpu_memcpy((u8 *)&ppwrpack->policies.hdr.data.global_ceiling,
(u8 *)&g->pmgr_pmu.pmgr_policyobjs.global_ceiling,
sizeof(struct nv_pmu_perf_domain_group_limits));
(void) memcpy(&ppwrpack->policies.hdr.data.semantic_policy_tbl,
&g->pmgr_pmu.pmgr_policyobjs.policy_idxs,
nvgpu_memcpy((u8 *)&ppwrpack->policies.hdr.data.semantic_policy_tbl,
(u8 *)&g->pmgr_pmu.pmgr_policyobjs.policy_idxs,
sizeof(g->pmgr_pmu.pmgr_policyobjs.policy_idxs));
BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(32, indx,

7
drivers/gpu/nvgpu/pmgr/pwrpolicy.c
View File

@@ -25,6 +25,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/string.h>
#include "pwrpolicy.h"
#include "gp106/bios_gp106.h"
@@ -225,7 +226,8 @@ static int _pwr_domains_pmudatainit_hw_threshold(struct gk20a *g,
PWR_POLICY_LIMIT_ID_CURR),
p_pwr_policy->limit_delta);
(void) memcpy(&pmu_pwr_policy->integral, &p_pwr_policy->integral,
nvgpu_memcpy((u8 *)&pmu_pwr_policy->integral,
(u8 *)&p_pwr_policy->integral,
sizeof(struct ctrl_pmgr_pwr_policy_info_integral));
pmu_pwr_policy->sample_mult = p_pwr_policy->sample_mult;
@@ -342,7 +344,8 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g,
pwrpolicyparams->limit_batt:
CTRL_PMGR_PWR_POLICY_LIMIT_MAX));
(void) memcpy(&pwrpolicy->integral, &pwrpolicyparams->integral,
nvgpu_memcpy((u8 *)&pwrpolicy->integral,
(u8 *)&pwrpolicyparams->integral,
sizeof(struct ctrl_pmgr_pwr_policy_info_integral));
pwrpolicyhwthreshold->threshold_idx = hwthreshold->threshold_idx;