gpu: nvgpu: Fix unicast register accesses for SM

In two places we used broadcast register as base, but added the
unicast offset to it. This causes the write to go well beyond
valid register range.

Change the broadcast base to use unicast base instead in sequence
to resume a single SM and to record error state of SM.

Bug 200256272

Change-Id: I4ca9af2bb5877dba20ab96575f5094d42949c9e2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry-picked from commit 04177b3414535ce5092c8baeae29883bada9d36c)
Reviewed-on: http://git-master/r/1306331
Reviewed-by: Automatic_Commit_Validation_User

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -8740,7 +8740,7 @@ void gk20a_resume_single_sm(struct gk20a *g,
 			gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(),
 			gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f());
 	gk20a_writel(g,
-		gr_gpcs_tpcs_sm_dbgr_control0_r() + offset, dbgr_control0);
+		gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0);
 
 	/* Run trigger */
 	dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f();

drivers/gpu/nvgpu/gm20b/gr_gm20b.c

@@ -1259,9 +1259,9 @@ static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
 	gr->sm_error_states[sm_id].hww_warp_esr_pc = gk20a_readl(g,
 			gr_gpc0_tpc0_sm_hww_warp_esr_pc_r() + offset);
 	gr->sm_error_states[sm_id].hww_global_esr_report_mask = gk20a_readl(g,
-		       gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() + offset);
+		       gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r() + offset);
 	gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g,
-			gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() + offset);
+			gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r() + offset);
 
 	mutex_unlock(&g->dbg_sessions_lock);
 

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h

@@ -3062,6 +3062,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(vo
 {
 	return 0x100000;
 }
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void)
+{
+	return 0x00504644;
+}
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
 {
 	return 0x00419e4c;
@@ -3094,6 +3098,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet
 {
 	return 0x40;
 }
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void)
+{
+	return 0x0050464c;
+}
 static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
 {
 	return 0x00419d0c;

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h

@@ -3298,6 +3298,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(vo
 {
 	return 0x100000;
 }
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void)
+{
+	return 0x00504644;
+}
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
 {
 	return 0x00419e4c;
@@ -3338,6 +3342,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet
 {
 	return 0x40;
 }
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void)
+{
+	return 0x0050464c;
+}
 static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
 {
 	return 0x00419d0c;

drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h

@@ -3418,6 +3418,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(vo
 {
 	return 0x100000;
 }
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void)
+{
+	return 0x00504644;
+}
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
 {
 	return 0x00419e4c;
@@ -3458,6 +3462,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet
 {
 	return 0x40;
 }
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void)
+{
+	return 0x0050464c;
+}
 static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
 {
 	return 0x00419d0c;