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gpu: nvgpu: Remove support for legacy mapping
Make NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL mandatory for all map IOCTLs. We'll clean up the legacy kernel code in subsequent patches. Remove support for NVGPU_AS_IOCTL_MAP_BUFFER. It has been superseded by NVGPU_AS_IOCTL_MAP_BUFFER_EX. Remove legacy definitions to nvgpu_map_buffer_args and the related flags, and update the in-kernel map calls accordingly by switching to the newer definitions. Bug 1902982 Change-Id: Ie9a7f02b8d5d0ec7c3722c4481afab6d39b4fbd0 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560932 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1279,7 +1279,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
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/* map backing store to gpu virtual space */
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vaddr = nvgpu_gmmu_map(ch->vm, &gr->compbit_store.mem,
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g->gr.compbit_store.mem.size,
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NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
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NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
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gk20a_mem_flag_read_only,
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false,
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gr->compbit_store.mem.aperture);
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@@ -88,8 +88,8 @@ static int gk20a_as_ioctl_map_buffer_ex(
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compressible_kind = args->compr_kind;
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incompressible_kind = args->incompr_kind;
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} else {
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compressible_kind = args->kind;
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incompressible_kind = NV_KIND_INVALID;
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/* unsupported, direct kind control must be used */
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return -EINVAL;
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}
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return nvgpu_vm_map_buffer(as_share->vm, args->dmabuf_fd,
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@@ -100,19 +100,6 @@ static int gk20a_as_ioctl_map_buffer_ex(
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NULL);
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}
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static int gk20a_as_ioctl_map_buffer(
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struct gk20a_as_share *as_share,
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struct nvgpu_as_map_buffer_args *args)
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{
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gk20a_dbg_fn("");
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return nvgpu_vm_map_buffer(as_share->vm, args->dmabuf_fd,
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&args->o_a.offset,
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args->flags, NV_KIND_DEFAULT,
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NV_KIND_DEFAULT,
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0, 0, NULL);
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/* args->o_a.offset will be set if !err */
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}
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static int gk20a_as_ioctl_unmap_buffer(
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struct gk20a_as_share *as_share,
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struct nvgpu_as_unmap_buffer_args *args)
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@@ -187,8 +174,9 @@ static int gk20a_as_ioctl_map_buffer_batch(
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compressible_kind = map_args.compr_kind;
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incompressible_kind = map_args.incompr_kind;
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} else {
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compressible_kind = map_args.kind;
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incompressible_kind = NV_KIND_INVALID;
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/* direct kind control must be used */
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err = -EINVAL;
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break;
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}
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err = nvgpu_vm_map_buffer(
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@@ -348,11 +336,6 @@ long gk20a_as_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
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err = gk20a_as_ioctl_free_space(as_share,
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(struct nvgpu_as_free_space_args *)buf);
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break;
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case NVGPU_AS_IOCTL_MAP_BUFFER:
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trace_gk20a_as_ioctl_map_buffer(g->name);
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err = gk20a_as_ioctl_map_buffer(as_share,
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(struct nvgpu_as_map_buffer_args *)buf);
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break;
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case NVGPU_AS_IOCTL_MAP_BUFFER_EX:
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trace_gk20a_as_ioctl_map_buffer(g->name);
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err = gk20a_as_ioctl_map_buffer_ex(as_share,
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@@ -680,7 +680,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
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.pgsz = pgsz_idx,
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.kind_v = kind_v,
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.ctag = (u64)ctag_offset * (u64)ctag_granularity,
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.cacheable = flags & NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
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.cacheable = flags & NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
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.rw_flag = rw_flag,
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.sparse = sparse,
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.priv = priv,
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@@ -1738,7 +1738,7 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
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pm_ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm,
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&pm_ctx->mem,
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pm_ctx->mem.size,
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NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
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NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
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gk20a_mem_flag_none, true,
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pm_ctx->mem.aperture);
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if (!pm_ctx->mem.gpu_va) {
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@@ -2633,7 +2633,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
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}
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gpu_va = nvgpu_gmmu_map(ch_vm, mem, mem->size,
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NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
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NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
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gk20a_mem_flag_none, true, mem->aperture);
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if (!gpu_va)
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goto clean_up;
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@@ -2651,7 +2651,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
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}
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gpu_va = nvgpu_gmmu_map(ch_vm, mem, mem->size,
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NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
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NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
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gk20a_mem_flag_none, false, mem->aperture);
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if (!gpu_va)
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goto clean_up;
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@@ -2669,7 +2669,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
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}
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gpu_va = nvgpu_gmmu_map(ch_vm, mem, mem->size,
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NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
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NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
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gk20a_mem_flag_none, true, mem->aperture);
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if (!gpu_va)
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goto clean_up;
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@@ -2736,7 +2736,7 @@ int gr_gk20a_alloc_gr_ctx(struct gk20a *g,
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gr_ctx->mem.gpu_va = nvgpu_gmmu_map(vm,
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&gr_ctx->mem,
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gr_ctx->mem.size,
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NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_FALSE,
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0, /* not GPU-cacheable */
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gk20a_mem_flag_none, true,
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gr_ctx->mem.aperture);
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if (!gr_ctx->mem.gpu_va)
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@@ -913,7 +913,7 @@ int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
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mem->gpu_va = nvgpu_gmmu_map(vm,
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mem,
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mem->aligned_size,
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NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
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NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE,
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gk20a_mem_flag_none,
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false,
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mem->aperture);
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@@ -169,8 +169,7 @@ u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
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p->pgsz_idx = pgsz_idx;
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p->iova = 0;
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p->kind = kind_v;
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p->cacheable =
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(flags & NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE) ? 1 : 0;
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p->cacheable = (flags & NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE) ? 1 : 0;
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p->prot = prot;
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p->ctag_offset = ctag_offset;
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p->clear_ctags = clear_ctags;
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@@ -153,8 +153,7 @@ u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
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p->pgsz_idx = pgsz_idx;
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p->iova = mapping ? 1 : 0;
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p->kind = kind_v;
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p->cacheable =
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(flags & NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE) ? 1 : 0;
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p->cacheable = (flags & NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE) ? 1 : 0;
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p->prot = prot;
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p->ctag_offset = ctag_offset;
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p->clear_ctags = clear_ctags;
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@@ -1461,27 +1461,6 @@ struct nvgpu_submit_gpfifo_args {
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struct nvgpu_fence fence;
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};
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struct nvgpu_map_buffer_args {
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__u32 flags;
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#define NVGPU_MAP_BUFFER_FLAGS_ALIGN 0x0
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#define NVGPU_MAP_BUFFER_FLAGS_OFFSET (1 << 0)
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#define NVGPU_MAP_BUFFER_FLAGS_KIND_PITCH 0x0
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#define NVGPU_MAP_BUFFER_FLAGS_KIND_SPECIFIED (1 << 1)
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#define NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_FALSE 0x0
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#define NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE (1 << 2)
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__u32 nvmap_handle;
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union {
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__u64 offset; /* valid if _offset flag given (in|out) */
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__u64 align; /* alignment multiple (0:={1 or n/a}) */
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} offset_alignment;
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__u32 kind;
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#define NVGPU_MAP_BUFFER_KIND_GENERIC_16BX2 0xfe
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};
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struct nvgpu_unmap_buffer_args {
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__u64 offset;
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};
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struct nvgpu_wait_args {
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#define NVGPU_WAIT_TYPE_NOTIFIER 0x0
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#define NVGPU_WAIT_TYPE_SEMAPHORE 0x1
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@@ -1789,22 +1768,12 @@ struct nvgpu_as_bind_channel_args {
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* chosen will be returned back to the caller in the 'page_size' parameter in
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* that case.
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*/
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struct nvgpu_as_map_buffer_args {
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__u32 flags; /* in/out */
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#define NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET (1 << 0)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE (1 << 2)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT (1 << 4)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE (1 << 5)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS (1 << 6)
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#define NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL (1 << 8)
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__u32 reserved; /* in */
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__u32 dmabuf_fd; /* in */
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__u32 page_size; /* inout, 0:= best fit to buffer */
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union {
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__u64 offset; /* inout, byte address valid iff _FIXED_OFFSET */
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__u64 align; /* in, alignment multiple (0:={1 or n/a}) */
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} o_a;
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};
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/*
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* Mapping dmabuf fds into an address space:
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@@ -1816,19 +1785,10 @@ struct nvgpu_as_map_buffer_args {
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* returned back to the caller in the 'page_size' parameter in that case.
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*/
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struct nvgpu_as_map_buffer_ex_args {
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/* NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL must be set */
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__u32 flags; /* in/out */
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#define NV_KIND_DEFAULT -1
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union {
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/*
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* Used if NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL
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* is not set.
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*/
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__s32 kind; /* in (-1 represents default) */
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/*
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* If NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL is
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* set, this is used, instead. The rules are:
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*
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* - If both compr_kind and incompr_kind are set
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* (i.e., value is other than NV_KIND_INVALID),
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* kernel attempts to use compr_kind first.
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@@ -1837,18 +1797,17 @@ struct nvgpu_as_map_buffer_ex_args {
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* comptags for the buffer. If successful,
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* compr_kind is used as the PTE kind.
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*
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* - If incompr_kind is set, kernel uses incompr_kind
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* as the PTE kind. Comptags are not allocated.
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* - If incompr_kind is set, kernel uses incompr_kind as the
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* PTE kind, if compr_kind cannot be used. Comptags are not
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* allocated.
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*
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* - If neither compr_kind or incompr_kind is set, the
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* map call will fail.
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*/
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#define NV_KIND_INVALID -1
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struct {
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__s16 compr_kind;
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__s16 incompr_kind;
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};
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};
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__u32 dmabuf_fd; /* in */
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__u32 page_size; /* inout, 0:= best fit to buffer */
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@@ -1975,7 +1934,7 @@ struct nvgpu_as_get_va_regions_args {
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};
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struct nvgpu_as_map_buffer_batch_args {
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__u64 unmaps; /* ptr to array of nvgpu_unmap_buffer_args */
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__u64 unmaps; /* ptr to array of nvgpu_as_unmap_buffer_args */
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__u64 maps; /* ptr to array of nvgpu_as_map_buffer_ex_args */
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__u32 num_unmaps; /* in: number of unmaps
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* out: on error, number of successful unmaps */
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