diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 1b7dd405d..f91ef1ba4 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -110,7 +110,7 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
 			gr_gk20a_ctx_patch_write(g, ch_ctx,
 				gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp +
 				proj_ppc_in_gpc_stride_v() * ppc_index,
-				gr->alpha_cb_default_size * gr->pes_tpc_count[ppc_index][gpc_index],
+				gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(),
 				patch);
 
 			attrib_offset_in_chunk += gr->attrib_cb_size *
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 72f1d68c7..02674d6be 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -2174,6 +2174,14 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
 {
 	return 0x005030f0;
 }
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
+{
+	return (v & 0x3fffff) << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
+{
+	return 0x00030000;
+}
 static inline u32 gr_gpccs_falcon_addr_r(void)
 {
 	return 0x0041a0ac;