diff --git a/drivers/gpu/nvgpu/common/gr/fecs_trace.c b/drivers/gpu/nvgpu/common/gr/fecs_trace.c
index 03944b53c..60f091aaa 100644
--- a/drivers/gpu/nvgpu/common/gr/fecs_trace.c
+++ b/drivers/gpu/nvgpu/common/gr/fecs_trace.c
@@ -272,7 +272,14 @@ int nvgpu_gr_fecs_trace_enable(struct gk20a *g)
 			g->ops.gr.fecs_trace.flush(g);
 
 		write = g->ops.gr.fecs_trace.get_write_index(g);
-		g->ops.gr.fecs_trace.set_read_index(g, write);
+
+		/*
+		 * For enabling FECS trace support, MAILBOX1's MSB (Bit 31:31)
+		 * should be set to 1. Bits 30:0 represents actual pointer
+		 * value.
+		 */
+		g->ops.gr.fecs_trace.set_read_index(g, write |
+			(BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT)));
 
 		err = nvgpu_thread_create(&trace->poll_task, g,
 				nvgpu_gr_fecs_trace_periodic_polling, __func__);
@@ -298,6 +305,13 @@ int nvgpu_gr_fecs_trace_disable(struct gk20a *g)
 	nvgpu_mutex_acquire(&trace->enable_lock);
 	trace->enable_count--;
 	if (trace->enable_count == 0U) {
+		/*
+		 * For disabling FECS trace support, MAILBOX1's MSB (Bit 31:31)
+		 * should be set to 0.
+		 */
+		g->ops.gr.fecs_trace.set_read_index(g,
+			g->ops.gr.fecs_trace.get_read_index(g) &
+			(~(BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT))));
 		nvgpu_thread_stop(&trace->poll_task);
 	}
 	nvgpu_mutex_release(&trace->enable_lock);
@@ -483,6 +497,8 @@ int nvgpu_gr_fecs_trace_poll(struct gk20a *g)
 	/* Ensure all FECS writes have made it to SYSMEM */
 	g->ops.mm.cache.fb_flush(g);
 
+	/* Bits 30:0 of MAILBOX1 represents actual read pointer value */
+	read = read & (~(BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT)));
 	while (read != write) {
 		cnt = nvgpu_gr_fecs_trace_ring_read(g, read, &vm_update_mask);
 		if (cnt <= 0) {
@@ -493,6 +509,13 @@ int nvgpu_gr_fecs_trace_poll(struct gk20a *g)
 		read = (read + 1) & (GK20A_FECS_TRACE_NUM_RECORDS - 1);
 	}
 
+	/*
+	 * In the next step, read pointer is going to be updated.
+	 * So, MSB of read pointer should be set back to 1. This will
+	 * keep FECS trace enabled.
+	 */
+	read = read | (BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT));
+
 	/* ensure FECS records has been updated before incrementing read index */
 	nvgpu_wmb();
 	g->ops.gr.fecs_trace.set_read_index(g, read);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/fecs_trace.h b/drivers/gpu/nvgpu/include/nvgpu/gr/fecs_trace.h
index 9a5990257..4390abd0c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gr/fecs_trace.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/fecs_trace.h
@@ -55,6 +55,7 @@
 	((p)->tag_bits[(n) / 64] &   (1 << ((n) & 63)))
 
 #define NVGPU_GPU_CTXSW_FILTER_SIZE (NVGPU_GPU_CTXSW_TAG_LAST + 1)
+#define NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT 31
 
 struct gk20a;
 struct nvgpu_mem;