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gpu: nvgpu: channel MISRA fix for Rule 17.7
Change gk20a_free_priv_cmdbuf from int to void type Rename gk20a_free_priv_cmdbuf -> nvgpu_channel_update_priv_cmd_q_and_free_entry channel_gk20a_free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_q free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_entry JIRA NVGPU-3388 JIRA NVGPU-3248 Change-Id: I32bc5686a280f72c7bba4ab2d37782e29117f596 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2114971 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -258,7 +258,7 @@ static int channel_sync_syncpt_incr_common(struct nvgpu_channel_sync *s,
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return 0;
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clean_up_priv_cmd:
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gk20a_free_priv_cmdbuf(c, incr_cmd);
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nvgpu_channel_update_priv_cmd_q_and_free_entry(c, incr_cmd);
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return err;
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}
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