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gpu: nvgpu: remove debugger check for cilp completion event

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We can trigger CILP only if SM debug mode is on.

So in fecs interrupt handler, we could have graphics context
running for which SM debug mode is disabled.
And in that case we skip posting of cilp completion
events to UMD.

But since CILP event was anyways triggered, we need to post
events to UMD irrespective of SM debug mode is enabled
at that point or not

Hence remove check gk20a_gr_sm_debugger_attached() for
posting events to UMD

Bug 200243092

Change-Id: I54ad205be11ec6d5034d524bfbb28f8a1fa72993
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1263591
(cherry picked from commit e6259e2d0d5a4bb5929e70e03e154f8b82ae3600)
Reviewed-on: http://git-master/r/1264780
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
This commit is contained in:
Deepak Nibade
2016-12-02 11:46:17 +05:30
parent d8dc7b130e
commit c320ccfa95
1 changed files with 9 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
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@@ -1896,7 +1896,7 @@ static int gr_gp10b_handle_fecs_error(struct gk20a *g,
goto clean_up; goto clean_up;
} }
if (gk20a_gr_sm_debugger_attached(g)) { /* Post events to UMD */
gk20a_dbg_gpu_post_events(ch); gk20a_dbg_gpu_post_events(ch);
if (gk20a_is_channel_marked_as_tsg(ch)) { if (gk20a_is_channel_marked_as_tsg(ch)) {
@@ -1908,7 +1908,6 @@ static int gr_gp10b_handle_fecs_error(struct gk20a *g,
gk20a_channel_event_id_post_event(ch, gk20a_channel_event_id_post_event(ch,
NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE);
} }
}
gk20a_channel_put(ch); gk20a_channel_put(ch);
} }