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gpu: nvgpu: add channel HAL section for ccsr_*

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Split out ops that belong to channel unit to a new section called
channel. Channel is a broad concept; this includes just the code that
accesses channel registers (ccsr_*). This is effectively just renaming;
the implementation still stays put.

The word "channel" is also dropped from certain HAL entries to avoid
redundancy (e.g., channel.disable_channel -> channel.disable).
fifo.get_num_fifos gets an entirely new name: channel.count.

Jira NVGPU-1307

Change-Id: I9a08103e461bf3ddb743aa37ababee3e0c73c861
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017261
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2019-02-12 13:05:13 +02:00
committed by mobile promotions
parent 1d49e8218d
commit c330d8fd98
18 changed files with 84 additions and 61 deletions
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8
drivers/gpu/nvgpu/os/linux/ioctl_channel.c
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@@ -1330,8 +1330,8 @@ long gk20a_channel_ioctl(struct file *filp,
__func__, cmd);
break;
}
if (ch->g->ops.fifo.enable_channel)
ch->g->ops.fifo.enable_channel(ch);
if (ch->g->ops.channel.enable)
ch->g->ops.channel.enable(ch);
else
err = -ENOSYS;
gk20a_idle(ch->g);
@@ -1344,8 +1344,8 @@ long gk20a_channel_ioctl(struct file *filp,
__func__, cmd);
break;
}
if (ch->g->ops.fifo.disable_channel)
ch->g->ops.fifo.disable_channel(ch);
if (ch->g->ops.channel.disable)
ch->g->ops.channel.disable(ch);
else
err = -ENOSYS;
gk20a_idle(ch->g);