From c33d9767da09c2819dd972f9d487a6a4434dda74 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 26 Mar 2019 11:46:10 +0530 Subject: [PATCH] gpu: nvgpu: ACR circular dependency clean up within ACR unit ACR WPR/blob-alloc functions are called from different parts of ACR UNIT like bootstrap, blob-construct & chip specific ACR sw init functions, these functions are part of acr.c which adds circular dependency between acr.c & other files, so, moved to respective new fiels based on its operation & also cleaned up header dependency. JIRA NVGPU-2907 Change-Id: I78d1eab59757029017d6ca62cbfc227a7a8240e4 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/2081632 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 2 + drivers/gpu/nvgpu/Makefile.sources | 2 + drivers/gpu/nvgpu/common/acr/acr.c | 49 -------- drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c | 62 ++++++++++ drivers/gpu/nvgpu/common/acr/acr_blob_alloc.h | 34 +++++ .../nvgpu/common/acr/acr_blob_construct_v0.c | 2 + .../nvgpu/common/acr/acr_blob_construct_v0.h | 44 +------ .../nvgpu/common/acr/acr_blob_construct_v1.c | 2 + .../nvgpu/common/acr/acr_blob_construct_v1.h | 18 +-- drivers/gpu/nvgpu/common/acr/acr_bootstrap.c | 1 + drivers/gpu/nvgpu/common/acr/acr_bootstrap.h | 75 ++++++----- drivers/gpu/nvgpu/common/acr/acr_falcon_bl.h | 116 ++++++++++++++++++ drivers/gpu/nvgpu/common/acr/acr_gm20b.c | 5 +- drivers/gpu/nvgpu/common/acr/acr_gv100.c | 6 +- drivers/gpu/nvgpu/common/acr/acr_gv11b.c | 6 +- drivers/gpu/nvgpu/common/acr/acr_priv.h | 57 +-------- drivers/gpu/nvgpu/common/acr/acr_tu104.c | 6 +- drivers/gpu/nvgpu/common/acr/acr_wpr.c | 42 +++++++ drivers/gpu/nvgpu/common/acr/acr_wpr.h | 38 ++++++ 19 files changed, 368 insertions(+), 199 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c create mode 100644 drivers/gpu/nvgpu/common/acr/acr_blob_alloc.h create mode 100644 drivers/gpu/nvgpu/common/acr/acr_falcon_bl.h create mode 100644 drivers/gpu/nvgpu/common/acr/acr_wpr.c create mode 100644 drivers/gpu/nvgpu/common/acr/acr_wpr.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index fba51ec7c..817fe6f0c 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -110,6 +110,8 @@ nvgpu-y += \ common/pmu/pmu_gv100.o \ common/pmu/pmu_tu104.o \ common/acr/acr.o \ + common/acr/acr_wpr.o \ + common/acr/acr_blob_alloc.o \ common/acr/acr_blob_construct_v0.o \ common/acr/acr_blob_construct_v1.o \ common/acr/acr_bootstrap.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index f26651e13..2a75290e9 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -142,6 +142,8 @@ srcs += common/sim.c \ common/pmu/pmu_gv100.c \ common/pmu/pmu_tu104.c \ common/acr/acr.c \ + common/acr/acr_wpr.c \ + common/acr/acr_blob_alloc.c \ common/acr/acr_blob_construct_v0.c \ common/acr/acr_blob_construct_v1.c \ common/acr/acr_bootstrap.c \ diff --git a/drivers/gpu/nvgpu/common/acr/acr.c b/drivers/gpu/nvgpu/common/acr/acr.c index 2b224ab02..9913385aa 100644 --- a/drivers/gpu/nvgpu/common/acr/acr.c +++ b/drivers/gpu/nvgpu/common/acr/acr.c @@ -32,55 +32,6 @@ #include "acr_gv100.h" #include "acr_tu104.h" -/* Both size and address of WPR need to be 128K-aligned */ -#define DGPU_WPR_SIZE 0x200000U - -/* ACR common API's used within ACR unit */ -int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size, - struct nvgpu_mem *mem) -{ - return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_PHYSICALLY_ADDRESSED, - size, mem); -} - -int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size, - struct nvgpu_mem *mem) -{ - struct wpr_carveout_info wpr_inf; - int err; - - if (mem->size != 0ULL) { - return 0; - } - - g->acr->get_wpr_info(g, &wpr_inf); - - /* - * Even though this mem_desc wouldn't be used, the wpr region needs to - * be reserved in the allocator. - */ - err = nvgpu_dma_alloc_vid_at(g, wpr_inf.size, - &g->acr->wpr_dummy, wpr_inf.wpr_base); - if (err != 0) { - return err; - } - - return nvgpu_dma_alloc_vid_at(g, wpr_inf.size, mem, - wpr_inf.nonwpr_base); -} - -void nvgpu_acr_wpr_info_sys(struct gk20a *g, struct wpr_carveout_info *inf) -{ - g->ops.fb.read_wpr_info(g, &inf->wpr_base, &inf->size); -} - -void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf) -{ - inf->wpr_base = g->mm.vidmem.bootstrap_base; - inf->nonwpr_base = inf->wpr_base + DGPU_WPR_SIZE; - inf->size = DGPU_WPR_SIZE; -} - /* ACR public API's */ bool nvgpu_acr_is_lsf_lazy_bootstrap(struct gk20a *g, struct nvgpu_acr *acr, u32 falcon_id) diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c b/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c new file mode 100644 index 000000000..7f2c99e3c --- /dev/null +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "acr_wpr.h" +#include "acr_priv.h" +#include "acr_blob_alloc.h" + +int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size, + struct nvgpu_mem *mem) +{ + return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_PHYSICALLY_ADDRESSED, + size, mem); +} + +int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size, + struct nvgpu_mem *mem) +{ + struct wpr_carveout_info wpr_inf; + int err; + + if (mem->size != 0ULL) { + return 0; + } + + g->acr->get_wpr_info(g, &wpr_inf); + + /* + * Even though this mem_desc wouldn't be used, the wpr region needs to + * be reserved in the allocator. + */ + err = nvgpu_dma_alloc_vid_at(g, wpr_inf.size, + &g->acr->wpr_dummy, wpr_inf.wpr_base); + if (err != 0) { + return err; + } + + return nvgpu_dma_alloc_vid_at(g, wpr_inf.size, mem, + wpr_inf.nonwpr_base); +} diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.h b/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.h new file mode 100644 index 000000000..ff51f54cd --- /dev/null +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_alloc.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef ACR_BLOB_ALLOC_H +#define ACR_BLOB_ALLOC_H + +struct gk20a; +struct nvgpu_mem; + +int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size, + struct nvgpu_mem *mem); +int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size, + struct nvgpu_mem *mem); + +#endif /* ACR_BLOB_ALLOC_H */ diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c index 1089bcf5d..e814ecf5e 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c @@ -29,6 +29,8 @@ #include #include "acr_blob_construct_v0.h" +#include "acr_falcon_bl.h" +#include "acr_wpr.h" #include "acr_priv.h" int nvgpu_acr_lsf_pmu_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img) diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.h b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.h index e533e0b6a..50875ddb3 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.h +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.h @@ -24,6 +24,9 @@ #define ACR_BLOB_CONSTRUCT_V0_H #include +#include + +#include "acr_falcon_bl.h" /* * Light Secure WPR Content Alignments @@ -114,47 +117,6 @@ struct lsf_lsb_header { u32 flags; }; -/* Falcon BL interfaces */ -/* - * Structure used by the boot-loader to load the rest of the code. This has - * to be filled by NVGPU and copied into DMEM at offset provided in the - * hsflcn_bl_desc.bl_desc_dmem_load_off. - */ -struct flcn_bl_dmem_desc { - u32 reserved[4]; /*Should be the first element..*/ - u32 signature[4]; /*Should be the first element..*/ - u32 ctx_dma; - u32 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - u32 data_dma_base; - u32 data_size; - u32 code_dma_base1; - u32 data_dma_base1; -}; - -/* - * Legacy structure used by the current PMU/DPU bootloader. - */ -struct loader_config { - u32 dma_idx; - u32 code_dma_base; /* upper 32-bits of 40-bit dma address */ - u32 code_size_total; - u32 code_size_to_load; - u32 code_entry_point; - u32 data_dma_base; /* upper 32-bits of 40-bit dma address */ - u32 data_size; /* initialized data of the application */ - u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */ - u32 argc; - u32 argv; - u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */ - u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */ - u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */ -}; - /* * Union of all supported structures used by bootloaders. */ diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c index 10a76b02a..ef2b1d89a 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c @@ -28,6 +28,8 @@ #include #include "acr_blob_construct_v1.h" +#include "acr_falcon_bl.h" +#include "acr_wpr.h" #include "acr_priv.h" static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value) diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h index 96e9e2881..74e6365c4 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h @@ -26,6 +26,8 @@ #include #include +#include "acr_falcon_bl.h" + /* * Light Secure WPR Content Alignments */ @@ -149,22 +151,6 @@ struct lsf_lsb_header_v1 { u32 flags; }; -struct flcn_bl_dmem_desc_v1 { - u32 reserved[4]; /*Should be the first element..*/ - u32 signature[4]; /*Should be the first element..*/ - u32 ctx_dma; - struct falc_u64 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - struct falc_u64 data_dma_base; - u32 data_size; - u32 argc; - u32 argv; -}; - #define UCODE_NB_MAX_DATE_LENGTH 64U struct ls_falcon_ucode_desc { u32 descriptor_size; diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c index 644556d6f..7b69c7380 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c +++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c @@ -30,6 +30,7 @@ #include #include +#include "acr_falcon_bl.h" #include "acr_bootstrap.h" #include "acr_priv.h" diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h index 2c5511484..f39290ea5 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h +++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h @@ -23,6 +23,11 @@ #ifndef ACR_BOOTSTRAP_H #define ACR_BOOTSTRAP_H +#include "acr_falcon_bl.h" + +struct gk20a; +struct nvgpu_acr; + /* * Supporting maximum of 2 regions. * This is needed to pre-allocate space in DMEM @@ -115,36 +120,6 @@ struct flcn_acr_desc_v1 { u32 dummy[4]; /* ACR_BSI_VPR_DESC */ }; -/* HS Falcon BL interfaces */ -/* - * The header used by NVGPU to figure out code and data sections of bootloader - * - * bl_code_off - Offset of code section in the image - * bl_code_size - Size of code section in the image - * bl_data_off - Offset of data section in the image - * bl_data_size - Size of data section in the image - */ -struct flcn_bl_img_hdr { - u32 bl_code_off; - u32 bl_code_size; - u32 bl_data_off; - u32 bl_data_size; -}; - -/* - * The descriptor used by NVGPU to figure out the requirements of bootloader - * - * bl_start_tag - Starting tag of bootloader - * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc - * to be loaded - * bl_img_hdr - Description of the image - */ -struct hsflcn_bl_desc { - u32 bl_start_tag; - u32 bl_desc_dmem_load_off; - struct flcn_bl_img_hdr bl_img_hdr; -}; - struct bin_hdr { /* 0x10de */ u32 bin_magic; @@ -185,5 +160,45 @@ struct acr_fw_header { u32 hdr_size; /* Size of above header */ }; +/* ACR Falcon descriptor's */ +struct hs_acr { +#define ACR_DEFAULT 0U +#define ACR_AHESASC 1U +#define ACR_ASB 2U + u32 acr_type; + + /* HS bootloader to validate & load ACR ucode */ + struct hs_flcn_bl acr_hs_bl; + + /* ACR ucode */ + const char *acr_fw_name; + struct nvgpu_firmware *acr_fw; + struct nvgpu_mem acr_ucode; + + union { + struct flcn_bl_dmem_desc bl_dmem_desc; + struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; + }; + + void *ptr_bl_dmem_desc; + u32 bl_dmem_desc_size; + + union{ + struct flcn_acr_desc *acr_dmem_desc; + struct flcn_acr_desc_v1 *acr_dmem_desc_v1; + }; + + /* Falcon used to execute ACR ucode */ + struct nvgpu_falcon *acr_flcn; + + void (*acr_flcn_setup_boot_config)(struct gk20a *g); + void (*report_acr_engine_bus_err_status)(struct gk20a *g, + u32 bar0_status, u32 error_type); + int (*acr_engine_bus_err_status)(struct gk20a *g, u32 *bar0_status, + u32 *error_type); +}; + +int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr, + struct hs_acr *acr_desc); #endif /* ACR_BOOTSTRAP_H */ diff --git a/drivers/gpu/nvgpu/common/acr/acr_falcon_bl.h b/drivers/gpu/nvgpu/common/acr/acr_falcon_bl.h new file mode 100644 index 000000000..2ce75cd8d --- /dev/null +++ b/drivers/gpu/nvgpu/common/acr/acr_falcon_bl.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef ACR_FALCON_BL_H +#define ACR_FALCON_BL_H + +#include + +/* Falcon BL interfaces */ +/* + * Structure used by the boot-loader to load the rest of the code. This has + * to be filled by NVGPU and copied into DMEM at offset provided in the + * hsflcn_bl_desc.bl_desc_dmem_load_off. + */ +struct flcn_bl_dmem_desc { + u32 reserved[4]; /*Should be the first element..*/ + u32 signature[4]; /*Should be the first element..*/ + u32 ctx_dma; + u32 code_dma_base; + u32 non_sec_code_off; + u32 non_sec_code_size; + u32 sec_code_off; + u32 sec_code_size; + u32 code_entry_point; + u32 data_dma_base; + u32 data_size; + u32 code_dma_base1; + u32 data_dma_base1; +}; + +struct flcn_bl_dmem_desc_v1 { + u32 reserved[4]; /*Should be the first element..*/ + u32 signature[4]; /*Should be the first element..*/ + u32 ctx_dma; + struct falc_u64 code_dma_base; + u32 non_sec_code_off; + u32 non_sec_code_size; + u32 sec_code_off; + u32 sec_code_size; + u32 code_entry_point; + struct falc_u64 data_dma_base; + u32 data_size; + u32 argc; + u32 argv; +}; + +/* HS Falcon BL interfaces */ +/* + * The header used by NVGPU to figure out code and data sections of bootloader + * + * bl_code_off - Offset of code section in the image + * bl_code_size - Size of code section in the image + * bl_data_off - Offset of data section in the image + * bl_data_size - Size of data section in the image + */ +struct flcn_bl_img_hdr { + u32 bl_code_off; + u32 bl_code_size; + u32 bl_data_off; + u32 bl_data_size; +}; + +/* + * The descriptor used by NVGPU to figure out the requirements of bootloader + * + * bl_start_tag - Starting tag of bootloader + * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc + * to be loaded + * bl_img_hdr - Description of the image + */ +struct hsflcn_bl_desc { + u32 bl_start_tag; + u32 bl_desc_dmem_load_off; + struct flcn_bl_img_hdr bl_img_hdr; +}; + +/* + * Legacy structure used by the current PMU bootloader. + */ +struct loader_config { + u32 dma_idx; + u32 code_dma_base; /* upper 32-bits of 40-bit dma address */ + u32 code_size_total; + u32 code_size_to_load; + u32 code_entry_point; + u32 data_dma_base; /* upper 32-bits of 40-bit dma address */ + u32 data_size; /* initialized data of the application */ + u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */ + u32 argc; + u32 argv; + u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */ + u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */ + u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */ +}; + + +#endif /* ACR_FALCON_BL_H */ diff --git a/drivers/gpu/nvgpu/common/acr/acr_gm20b.c b/drivers/gpu/nvgpu/common/acr/acr_gm20b.c index 2b0f9d2ab..f80063ab5 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_gm20b.c +++ b/drivers/gpu/nvgpu/common/acr/acr_gm20b.c @@ -28,9 +28,12 @@ #include "common/pmu/pmu_gm20b.h" -#include "acr_blob_construct_v0.h" +#include "acr_wpr.h" #include "acr_priv.h" #include "acr_gm20b.h" +#include "acr_blob_alloc.h" +#include "acr_bootstrap.h" +#include "acr_blob_construct_v0.h" static int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery) diff --git a/drivers/gpu/nvgpu/common/acr/acr_gv100.c b/drivers/gpu/nvgpu/common/acr/acr_gv100.c index a4255798a..fffdfe262 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_gv100.c +++ b/drivers/gpu/nvgpu/common/acr/acr_gv100.c @@ -24,13 +24,15 @@ #include #include -#include "acr_blob_construct_v1.h" +#include "acr_wpr.h" #include "acr_priv.h" #include "acr_gv100.h" +#include "acr_blob_alloc.h" +#include "acr_bootstrap.h" +#include "acr_blob_construct_v1.h" #include "gp106/sec2_gp106.h" - static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value) { dma_addr->lo |= u64_lo32(value); diff --git a/drivers/gpu/nvgpu/common/acr/acr_gv11b.c b/drivers/gpu/nvgpu/common/acr/acr_gv11b.c index 4caa131f9..e99713aba 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_gv11b.c +++ b/drivers/gpu/nvgpu/common/acr/acr_gv11b.c @@ -27,9 +27,11 @@ #include "common/pmu/pmu_gm20b.h" -#include "acr_blob_construct_v1.h" +#include "acr_wpr.h" #include "acr_priv.h" - +#include "acr_blob_alloc.h" +#include "acr_blob_construct_v1.h" +#include "acr_bootstrap.h" #include "acr_gm20b.h" #include "acr_gv100.h" #include "acr_gv11b.h" diff --git a/drivers/gpu/nvgpu/common/acr/acr_priv.h b/drivers/gpu/nvgpu/common/acr/acr_priv.h index 1e47d0a56..39da4a0bb 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_priv.h +++ b/drivers/gpu/nvgpu/common/acr/acr_priv.h @@ -23,9 +23,6 @@ #ifndef ACR_H #define ACR_H -#include -#include - #include "acr_bootstrap.h" #include "acr_blob_construct_v0.h" #include "acr_blob_construct_v1.h" @@ -33,6 +30,7 @@ struct nvgpu_firmware; struct gk20a; struct nvgpu_acr; +struct wpr_carveout_info; #define nvgpu_acr_dbg(g, fmt, args...) \ nvgpu_log(g, gpu_dbg_pmu, fmt, ##args) @@ -94,50 +92,6 @@ struct nvgpu_acr; #define ACR_COMPLETION_TIMEOUT_MS 10000U /*in msec */ -struct wpr_carveout_info { - u64 wpr_base; - u64 nonwpr_base; - u64 size; -}; - -/* ACR Falcon descriptor's */ -struct hs_acr { -#define ACR_DEFAULT 0U -#define ACR_AHESASC 1U -#define ACR_ASB 2U - u32 acr_type; - - /* HS bootloader to validate & load ACR ucode */ - struct hs_flcn_bl acr_hs_bl; - - /* ACR ucode */ - const char *acr_fw_name; - struct nvgpu_firmware *acr_fw; - struct nvgpu_mem acr_ucode; - - union { - struct flcn_bl_dmem_desc bl_dmem_desc; - struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; - }; - - void *ptr_bl_dmem_desc; - u32 bl_dmem_desc_size; - - union{ - struct flcn_acr_desc *acr_dmem_desc; - struct flcn_acr_desc_v1 *acr_dmem_desc_v1; - }; - - /* Falcon used to execute ACR ucode */ - struct nvgpu_falcon *acr_flcn; - - void (*acr_flcn_setup_boot_config)(struct gk20a *g); - void (*report_acr_engine_bus_err_status)(struct gk20a *g, - u32 bar0_status, u32 error_type); - int (*acr_engine_bus_err_status)(struct gk20a *g, u32 *bar0_status, - u32 *error_type); -}; - struct acr_lsf_config { u32 falcon_id; u32 falcon_dma_idx; @@ -190,13 +144,4 @@ struct nvgpu_acr { void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf); }; -int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr, - struct hs_acr *acr_desc); -int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size, - struct nvgpu_mem *mem); -int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size, - struct nvgpu_mem *mem); -void nvgpu_acr_wpr_info_sys(struct gk20a *g, struct wpr_carveout_info *inf); -void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf); - #endif /* ACR_H */ diff --git a/drivers/gpu/nvgpu/common/acr/acr_tu104.c b/drivers/gpu/nvgpu/common/acr/acr_tu104.c index 3c85cb272..f49d53ad5 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_tu104.c +++ b/drivers/gpu/nvgpu/common/acr/acr_tu104.c @@ -24,14 +24,16 @@ #include #include -#include "acr_blob_construct_v1.h" +#include "acr_wpr.h" #include "acr_priv.h" +#include "acr_blob_alloc.h" +#include "acr_bootstrap.h" +#include "acr_blob_construct_v1.h" #include "acr_gv100.h" #include "acr_tu104.h" #include "tu104/sec2_tu104.h" - static int tu104_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr, struct hs_acr *acr_type) { diff --git a/drivers/gpu/nvgpu/common/acr/acr_wpr.c b/drivers/gpu/nvgpu/common/acr/acr_wpr.c new file mode 100644 index 000000000..de14ee230 --- /dev/null +++ b/drivers/gpu/nvgpu/common/acr/acr_wpr.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "acr_wpr.h" + +/* Both size and address of WPR need to be 128K-aligned */ +#define DGPU_WPR_SIZE 0x200000U + +void nvgpu_acr_wpr_info_sys(struct gk20a *g, struct wpr_carveout_info *inf) +{ + g->ops.fb.read_wpr_info(g, &inf->wpr_base, &inf->size); +} + +void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf) +{ + inf->wpr_base = g->mm.vidmem.bootstrap_base; + inf->nonwpr_base = inf->wpr_base + DGPU_WPR_SIZE; + inf->size = DGPU_WPR_SIZE; +} diff --git a/drivers/gpu/nvgpu/common/acr/acr_wpr.h b/drivers/gpu/nvgpu/common/acr/acr_wpr.h new file mode 100644 index 000000000..d60140285 --- /dev/null +++ b/drivers/gpu/nvgpu/common/acr/acr_wpr.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef ACR_WPR_H +#define ACR_WPR_H + +struct gk20a; +struct wpr_carveout_info; + +struct wpr_carveout_info { + u64 wpr_base; + u64 nonwpr_base; + u64 size; +}; + +void nvgpu_acr_wpr_info_sys(struct gk20a *g, struct wpr_carveout_info *inf); +void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf); + +#endif /* NVGPU_ACR_WPR_H */