gpu: nvgpu: gk20a: fix MISRA 10.4 Violations [2/2]

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: I4c04e2720a3b068909cc4af6847d4718568c13ea
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822740
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sai Nikhil
2018-11-09 12:50:35 +05:30
committed by mobile promotions
parent 94e00ab6ad
commit c365698e18
12 changed files with 253 additions and 253 deletions

View File

@@ -46,7 +46,7 @@
/*
* Copy engine defines line size in pixels
*/
#define MAX_CE_SHIFT 31 /* 4Gpixels -1 */
#define MAX_CE_SHIFT 31U /* 4Gpixels -1 */
#define MAX_CE_MASK ((u32) (~(~0U << MAX_CE_SHIFT)))
#define MAX_CE_ALIGN(a) ((a) & MAX_CE_MASK)
@@ -270,7 +270,7 @@ int gk20a_ce_prepare_submit(u64 src_buf,
cmd_buf_cpu_va[methodSize++] = 0x00000001;
}
launch |= 0x00001000;
launch |= 0x00001000U;
} else if (request_operation & NVGPU_CE_MEMSET) {
/* Remap from component A on 1 byte wide pixels */
cmd_buf_cpu_va[methodSize++] = 0x200181c2;
@@ -279,7 +279,7 @@ int gk20a_ce_prepare_submit(u64 src_buf,
cmd_buf_cpu_va[methodSize++] = 0x200181c0;
cmd_buf_cpu_va[methodSize++] = payload;
launch |= 0x00000400;
launch |= 0x00000400U;
} else {
/* Illegal size */
return 0;
@@ -308,18 +308,18 @@ int gk20a_ce_prepare_submit(u64 src_buf,
cmd_buf_cpu_va[methodSize++] = 0x00000001;
}
launch |= 0x00002005;
launch |= 0x00002005U;
if (launch_flags & NVGPU_CE_SRC_MEMORY_LAYOUT_BLOCKLINEAR) {
launch |= 0x00000000;
launch |= 0x00000000U;
} else {
launch |= 0x00000080;
launch |= 0x00000080U;
}
if (launch_flags & NVGPU_CE_DST_MEMORY_LAYOUT_BLOCKLINEAR) {
launch |= 0x00000000;
launch |= 0x00000000U;
} else {
launch |= 0x00000100;
launch |= 0x00000100U;
}
cmd_buf_cpu_va[methodSize++] = 0x200180c0;