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gpu: nvgpu: gk20a: fix MISRA 10.4 Violations [2/2]
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: I4c04e2720a3b068909cc4af6847d4718568c13ea Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822740 GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -46,7 +46,7 @@
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/*
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* Copy engine defines line size in pixels
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*/
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#define MAX_CE_SHIFT 31 /* 4Gpixels -1 */
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#define MAX_CE_SHIFT 31U /* 4Gpixels -1 */
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#define MAX_CE_MASK ((u32) (~(~0U << MAX_CE_SHIFT)))
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#define MAX_CE_ALIGN(a) ((a) & MAX_CE_MASK)
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@@ -270,7 +270,7 @@ int gk20a_ce_prepare_submit(u64 src_buf,
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cmd_buf_cpu_va[methodSize++] = 0x00000001;
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}
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launch |= 0x00001000;
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launch |= 0x00001000U;
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} else if (request_operation & NVGPU_CE_MEMSET) {
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/* Remap from component A on 1 byte wide pixels */
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cmd_buf_cpu_va[methodSize++] = 0x200181c2;
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@@ -279,7 +279,7 @@ int gk20a_ce_prepare_submit(u64 src_buf,
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cmd_buf_cpu_va[methodSize++] = 0x200181c0;
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cmd_buf_cpu_va[methodSize++] = payload;
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launch |= 0x00000400;
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launch |= 0x00000400U;
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} else {
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/* Illegal size */
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return 0;
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@@ -308,18 +308,18 @@ int gk20a_ce_prepare_submit(u64 src_buf,
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cmd_buf_cpu_va[methodSize++] = 0x00000001;
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}
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launch |= 0x00002005;
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launch |= 0x00002005U;
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if (launch_flags & NVGPU_CE_SRC_MEMORY_LAYOUT_BLOCKLINEAR) {
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launch |= 0x00000000;
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launch |= 0x00000000U;
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} else {
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launch |= 0x00000080;
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launch |= 0x00000080U;
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}
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if (launch_flags & NVGPU_CE_DST_MEMORY_LAYOUT_BLOCKLINEAR) {
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launch |= 0x00000000;
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launch |= 0x00000000U;
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} else {
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launch |= 0x00000100;
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launch |= 0x00000100U;
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}
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cmd_buf_cpu_va[methodSize++] = 0x200180c0;
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