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gpu: nvgpu: sim: make ring buffer independent of PAGE_SIZE

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The simulator ring buffer DMA interface supports buffers of the following sizes:
4, 8, 12 and 16K. At present, it is configured to 4K and it  happens to match
with the kernel PAGE_SIZE, which is used to wrap back the GET/PUT pointers once
4K is reached. However, this is not always true; for instance, take 64K pages.
Hence, replace PAGE_SIZE with SIM_BFR_SIZE.

Introduce macro NVGPU_CPU_PAGE_SIZE which aliases to PAGE_SIZE and replace
latter with former.

Bug 200658101
Jira NVGPU-6018

Change-Id: I83cc62b87291734015c51f3e5a98173549e065de
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420728
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2020-09-28 16:44:40 +05:30
committed by Alex Waterman
parent 09857ecd91
commit c36752fe3d
37 changed files with 120 additions and 103 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/semaphore/semaphore_hw.c
View File

@@ -46,7 +46,7 @@ int nvgpu_hw_semaphore_init(struct vm_gk20a *vm, u32 chid,
/* Find an available HW semaphore. */
hw_sema_idx = semaphore_bitmap_alloc(p->semas_alloced,
PAGE_SIZE / SEMAPHORE_SIZE);
NVGPU_CPU_PAGE_SIZE / SEMAPHORE_SIZE);
if (hw_sema_idx < 0) {
ret = hw_sema_idx;
goto fail;

4
drivers/gpu/nvgpu/common/semaphore/semaphore_pool.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -244,7 +244,7 @@ u64 nvgpu_semaphore_pool_gpu_va(struct nvgpu_semaphore_pool *p, bool global)
return p->gpu_va;
}
return p->gpu_va_ro + (PAGE_SIZE * p->page_idx);
return p->gpu_va_ro + (NVGPU_CPU_PAGE_SIZE * p->page_idx);
}
/*

2
drivers/gpu/nvgpu/common/semaphore/semaphore_priv.h
View File

@@ -93,7 +93,7 @@ struct nvgpu_semaphore_pool {
u64 gpu_va_ro; /* GPU access to the pool. */
u64 page_idx; /* Index into sea bitmap. */
DECLARE_BITMAP(semas_alloced, PAGE_SIZE / SEMAPHORE_SIZE);
DECLARE_BITMAP(semas_alloced, NVGPU_CPU_PAGE_SIZE / SEMAPHORE_SIZE);
struct nvgpu_semaphore_sea *sema_sea; /* Sea that owns this pool. */

8
drivers/gpu/nvgpu/common/semaphore/semaphore_sea.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -50,21 +50,21 @@ static int semaphore_sea_grow(struct nvgpu_semaphore_sea *sea)
nvgpu_semaphore_sea_lock(sea);
ret = nvgpu_dma_alloc_sys(g,
PAGE_SIZE * SEMAPHORE_POOL_COUNT,
NVGPU_CPU_PAGE_SIZE * SEMAPHORE_POOL_COUNT,
&sea->sea_mem);
if (ret != 0) {
goto out;
}
sea->size = SEMAPHORE_POOL_COUNT;
sea->map_size = SEMAPHORE_POOL_COUNT * PAGE_SIZE;
sea->map_size = SEMAPHORE_POOL_COUNT * NVGPU_CPU_PAGE_SIZE;
/*
* Start the semaphores at values that will soon overflow the 32-bit
* integer range. This way any buggy comparisons would start to fail
* sooner rather than later.
*/
for (i = 0U; i < PAGE_SIZE * SEMAPHORE_POOL_COUNT; i += 4U) {
for (i = 0U; i < NVGPU_CPU_PAGE_SIZE * SEMAPHORE_POOL_COUNT; i += 4U) {
nvgpu_mem_wr(g, &sea->sea_mem, i, 0xfffffff0U);
}