diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index fd31ab894..5d428afa8 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -36,6 +36,27 @@
 #include <nvgpu/hw/gk20a/hw_therm_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_perf_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
+
+static void gk20a_perfbuf_reset_streaming(struct gk20a *g)
+{
+	u32 engine_status;
+	u32 num_unread_bytes;
+
+	g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+
+	engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r());
+	WARN_ON(0u ==
+		(engine_status & perf_pmasys_enginestatus_rbufempty_empty_f()));
+
+	gk20a_writel(g, perf_pmasys_control_r(),
+		perf_pmasys_control_membuf_clear_status_doit_f());
+
+	num_unread_bytes = gk20a_readl(g, perf_pmasys_mem_bytes_r());
+	if (num_unread_bytes != 0u) {
+		gk20a_writel(g, perf_pmasys_mem_bump_r(), num_unread_bytes);
+	}
+}
 
 /*
  * API to get first channel from the list of all channels
@@ -316,6 +337,8 @@ int gk20a_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size)
 
 	g->ops.mm.init_inst_block(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0);
 
+	gk20a_perfbuf_reset_streaming(g);
+
 	virt_addr_lo = u64_lo32(offset);
 	virt_addr_hi = u64_hi32(offset);
 
@@ -349,6 +372,8 @@ int gk20a_perfbuf_disable_locked(struct gk20a *g)
 		return err;
 	}
 
+	gk20a_perfbuf_reset_streaming(g);
+
 	gk20a_writel(g, perf_pmasys_outbase_r(), 0);
 	gk20a_writel(g, perf_pmasys_outbaseupper_r(),
 			perf_pmasys_outbaseupper_ptr_f(0));
diff --git a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c
index 562476ca8..0dad7c2d5 100644
--- a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c
@@ -25,6 +25,27 @@
 #include <nvgpu/log.h>
 #include "gk20a/gk20a.h"
 #include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
+
+static void gv11b_perfbuf_reset_streaming(struct gk20a *g)
+{
+	u32 engine_status;
+	u32 num_unread_bytes;
+
+	g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+
+	engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r());
+	WARN_ON(0u ==
+		(engine_status & perf_pmasys_enginestatus_rbufempty_empty_f()));
+
+	gk20a_writel(g, perf_pmasys_control_r(),
+		perf_pmasys_control_membuf_clear_status_doit_f());
+
+	num_unread_bytes = gk20a_readl(g, perf_pmasys_mem_bytes_r());
+	if (num_unread_bytes != 0u) {
+		gk20a_writel(g, perf_pmasys_mem_bump_r(), num_unread_bytes);
+	}
+}
 
 int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size)
 {
@@ -47,6 +68,8 @@ int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size)
 
 	g->ops.mm.init_inst_block(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0);
 
+	gv11b_perfbuf_reset_streaming(g);
+
 	virt_addr_lo = u64_lo32(offset);
 	virt_addr_hi = u64_hi32(offset);
 
@@ -82,6 +105,8 @@ int gv11b_perfbuf_disable_locked(struct gk20a *g)
 		return err;
 	}
 
+	gv11b_perfbuf_reset_streaming(g);
+
 	gk20a_writel(g, perf_pmasys_outbase_r(), 0);
 	gk20a_writel(g, perf_pmasys_outbaseupper_r(),
 			perf_pmasys_outbaseupper_ptr_f(0));