From c3c541b1af82f510f316fb40415062c0956f831b Mon Sep 17 00:00:00 2001 From: Vinod G Date: Mon, 10 Jun 2019 13:21:16 -0700 Subject: [PATCH] gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.ecc unit Fix CERT INT30-C erros in hal.gr.ecc units. Unsigned integer operation may wrap. Use safe_ops macro to fix the wrap errors. Jira NVGPU-3585 Change-Id: I3811bfe0c542e7960ab8dbc2877465f7a72d1761 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/2133803 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Nitin Kumbhar GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b.c b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b.c index d708c23c5..6b2712fbc 100644 --- a/drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b.c @@ -90,7 +90,8 @@ int gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g, { unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); unsigned int gpc = (error_info & 0xFFU); - unsigned int reg_addr = err->get_reg_addr() + gpc * gpc_stride; + unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(), + nvgpu_safe_mult_u32(gpc , gpc_stride)); nvgpu_info(g, "Injecting GPCCS fault %s for gpc: %d", err->name, gpc); nvgpu_writel(g, reg_addr, err->get_reg_val(1U)); @@ -147,8 +148,10 @@ int gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g, nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); unsigned int gpc = (error_info & 0xFF00U) >> 8U; unsigned int tpc = (error_info & 0xFFU); - unsigned int reg_addr = err->get_reg_addr() + gpc * gpc_stride - + tpc * tpc_stride; + unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(), + nvgpu_safe_add_u32( + nvgpu_safe_mult_u32(gpc , gpc_stride), + nvgpu_safe_mult_u32(tpc , tpc_stride))); nvgpu_info(g, "Injecting SM fault %s for gpc: %d, tpc: %d", err->name, gpc, tpc); @@ -182,7 +185,8 @@ int gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g, { unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); unsigned int gpc = (error_info & 0xFFU); - unsigned int reg_addr = err->get_reg_addr() + gpc * gpc_stride; + unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(), + nvgpu_safe_mult_u32(gpc , gpc_stride)); nvgpu_info(g, "Injecting MMU fault %s for gpc: %d", err->name, gpc); nvgpu_writel(g, reg_addr, err->get_reg_val(1U)); @@ -216,8 +220,8 @@ int gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g, unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); unsigned int gpc = (error_info & 0xFFU); - unsigned int reg_addr = err->get_reg_addr() - + gpc * gpc_stride; + unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(), + nvgpu_safe_mult_u32(gpc , gpc_stride)); nvgpu_info(g, "Injecting GCC fault %s for gpc: %d", err->name, gpc); nvgpu_writel(g, reg_addr, err->get_reg_val(1U));