diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk index d53d8a1ad..2c100cc48 100644 --- a/Makefile.umbrella.tmk +++ b/Makefile.umbrella.tmk @@ -67,6 +67,10 @@ NV_REPOSITORY_COMPONENTS += userspace/units/mm/gmmu/pd_cache NV_REPOSITORY_COMPONENTS += userspace/units/mm/gmmu/page_table NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/cache/flush_gk20a_fusa NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/cache/flush_gv11b_fusa +NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa +NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa +NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa +NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/gp10b_fusa NV_REPOSITORY_COMPONENTS += userspace/units/mm/hal/gv11b_fusa NV_REPOSITORY_COMPONENTS += userspace/units/mm/mm diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export index 9d5af62bf..cf72349f9 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export @@ -20,6 +20,8 @@ gk20a_fifo_intr_1_isr gk20a_fifo_intr_handle_chsw_error gk20a_fifo_intr_handle_runlist_event gk20a_fifo_pbdma_isr +gk20a_get_pde_pgsz +gk20a_get_pte_pgsz gk20a_mm_fb_flush gk20a_mm_l2_flush gk20a_mm_l2_invalidate diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index 3079658e2..03f02ade6 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -74,6 +74,10 @@ UNITS := \ $(UNIT_SRC)/mm/gmmu/page_table \ $(UNIT_SRC)/mm/hal/cache/flush_gk20a_fusa \ $(UNIT_SRC)/mm/hal/cache/flush_gv11b_fusa \ + $(UNIT_SRC)/mm/hal/gmmu/gmmu_gk20a_fusa \ + $(UNIT_SRC)/mm/hal/gmmu/gmmu_gm20b_fusa \ + $(UNIT_SRC)/mm/hal/gmmu/gmmu_gp10b_fusa \ + $(UNIT_SRC)/mm/hal/gmmu/gmmu_gv11b_fusa \ $(UNIT_SRC)/mm/hal/gp10b_fusa \ $(UNIT_SRC)/mm/hal/gv11b_fusa \ $(UNIT_SRC)/mm/mm \ diff --git a/userspace/SWUTS.h b/userspace/SWUTS.h index e9f4b525b..98a594cdb 100644 --- a/userspace/SWUTS.h +++ b/userspace/SWUTS.h @@ -70,6 +70,10 @@ * - @ref SWUTS-mm-gmmu-page_table * - @ref SWUTS-mm-hal-cache-flush-gk20a-fusa * - @ref SWUTS-mm-hal-cache-flush-gv11b-fusa + * - @ref SWUTS-mm-hal-gmmu-gmmu_gk20a_fusa + * - @ref SWUTS-mm-hal-gmmu-gmmu_gm20b_fusa + * - @ref SWUTS-mm-hal-gmmu-gmmu_gp10b_fusa + * - @ref SWUTS-mm-hal-gmmu-gmmu_gv11b_fusa * - @ref SWUTS-mm-hal-gp10b_fusa * - @ref SWUTS-mm-hal-gv11b-fusa * - @ref SWUTS-mm-nvgpu-mem diff --git a/userspace/SWUTS.sources b/userspace/SWUTS.sources index 73097ef5b..e5562b28b 100644 --- a/userspace/SWUTS.sources +++ b/userspace/SWUTS.sources @@ -46,6 +46,10 @@ INPUT += ../../../userspace/units/mm/dma/dma.h INPUT += ../../../userspace/units/mm/gmmu/page_table/page_table.h INPUT += ../../../userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.h INPUT += ../../../userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gv11b-fusa.h +INPUT += ../../../userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/gmmu-gk20a-fusa.h +INPUT += ../../../userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/gmmu-gm20b-fusa.h +INPUT += ../../../userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.h +INPUT += ../../../userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/gmmu-gv11b-fusa.h INPUT += ../../../userspace/units/mm/hal/gp10b_fusa/mm-gp10b-fusa.h INPUT += ../../../userspace/units/mm/hal/gv11b_fusa/mm-gv11b-fusa.h INPUT += ../../../userspace/units/mm/nvgpu_mem/nvgpu_mem.h diff --git a/userspace/required_tests.json b/userspace/required_tests.json index 8c2c5a168..d192a5e51 100644 --- a/userspace/required_tests.json +++ b/userspace/required_tests.json @@ -935,6 +935,168 @@ "unit": "fuse", "test_level": 0 }, + { + "test": "test_gk20a_get_pde_pgsz", + "case": "pde_pgsz", + "unit": "gmmu_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gk20a_get_pte_pgsz", + "case": "pte_pgsz", + "unit": "gmmu_gk20a_fusa", + "test_level": 0 + }, + { + "test": "test_gm20b_mm_get_big_page_sizes", + "case": "get_big_pgsz", + "unit": "gmmu_gm20b_fusa", + "test_level": 0 + }, + { + "test": "test_gp10b_mm_get_default_big_page_size", + "case": "big_pgsz", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_gp10b_get_pde0_pgsz", + "case": "gp10b_get_pde0_pgsz_s0", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_gp10b_get_pde0_pgsz", + "case": "gp10b_get_pde0_pgsz_s1", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_gp10b_get_pde0_pgsz", + "case": "gp10b_get_pde0_pgsz_s2", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_gp10b_get_pde0_pgsz", + "case": "gp10b_get_pde0_pgsz_s3", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_gp10b_get_pde0_pgsz", + "case": "gp10b_get_pde0_pgsz_s4", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_gp10b_get_pde0_pgsz", + "case": "gp10b_get_pde0_pgsz_s5", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_gp10b_mm_get_iommu_bit", + "case": "iommu_bit", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_gp10b_get_max_page_table_levels", + "case": "max_page_table_levels", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_gp10b_mm_get_mmu_levels", + "case": "mmu_levels", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pde0_locked", + "case": "update_gmmu_pde0_locked_s0", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pde0_locked", + "case": "update_gmmu_pde0_locked_s1", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pde3_locked", + "case": "update_gmmu_pde3_locked", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pte_locked", + "case": "update_gmmu_pte_locked_s0", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pte_locked", + "case": "update_gmmu_pte_locked_s1", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pte_locked", + "case": "update_gmmu_pte_locked_s2", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pte_locked", + "case": "update_gmmu_pte_locked_s3", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pte_locked", + "case": "update_gmmu_pte_locked_s4", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pte_locked", + "case": "update_gmmu_pte_locked_s5", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pte_locked", + "case": "update_gmmu_pte_locked_s6", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_update_gmmu_pte_locked", + "case": "update_gmmu_pte_locked_s7", + "unit": "gmmu_gp10b_fusa", + "test_level": 0 + }, + { + "test": "test_gv11b_gpu_phys_addr", + "case": "gpu_phys_addr_s0", + "unit": "gmmu_gv11b_fusa", + "test_level": 0 + }, + { + "test": "test_gv11b_gpu_phys_addr", + "case": "gpu_phys_addr_s1", + "unit": "gmmu_gv11b_fusa", + "test_level": 0 + }, + { + "test": "test_gv11b_gpu_phys_addr", + "case": "gpu_phys_addr_s2", + "unit": "gmmu_gv11b_fusa", + "test_level": 0 + }, { "test": "test_get_litter_value", "case": "get_litter_value", diff --git a/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile b/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile new file mode 100644 index 000000000..40225cf24 --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile @@ -0,0 +1,26 @@ +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = gmmu-gk20a-fusa.o +MODULE = gmmu-gk20a-fusa + +include ../../../../Makefile.units diff --git a/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile.interface.tmk b/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile.interface.tmk new file mode 100644 index 000000000..00fd8ab17 --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=gmmu-gk20a-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile.tmk b/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile.tmk new file mode 100644 index 000000000..1a8f788a8 --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=gmmu-gk20a-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/gmmu-gk20a-fusa.c b/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/gmmu-gk20a-fusa.c new file mode 100644 index 000000000..a2ab962fb --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/gmmu-gk20a-fusa.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include +#include + +#include +#include +#include "hal/mm/gmmu/gmmu_gk20a.h" + +#include "gmmu-gk20a-fusa.h" + +int test_gk20a_get_pde_pgsz(struct unit_module *m, struct gk20a *g, void *args) +{ + struct gk20a_mmu_level l; + struct nvgpu_gmmu_pd pd; + u32 ret_pgsz; + int ret = UNIT_FAIL; + + ret_pgsz = gk20a_get_pde_pgsz(g, &l, &pd, 0U); + unit_assert(ret_pgsz == GMMU_PAGE_SIZE_SMALL, goto done); + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s pde_pgsz != GMMU_PAGE_SIZE_SMALL as expected\n", + __func__); + } + + return ret; +} + +int test_gk20a_get_pte_pgsz(struct unit_module *m, struct gk20a *g, void *args) +{ + struct gk20a_mmu_level l; + struct nvgpu_gmmu_pd pd; + u32 ret_pgsz; + int ret = UNIT_FAIL; + + ret_pgsz = gk20a_get_pte_pgsz(g, &l, &pd, 0U); + unit_assert(ret_pgsz == GMMU_NR_PAGE_SIZES, goto done); + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s pte_pgsz != GMMU_NR_PAGE_SIZES as expected\n", + __func__); + } + + return ret; +} + +struct unit_module_test mm_gmmu_gk20a_fusa_tests[] = { + UNIT_TEST(pde_pgsz, test_gk20a_get_pde_pgsz, NULL, 0), + UNIT_TEST(pte_pgsz, test_gk20a_get_pte_pgsz, NULL, 0), +}; + +UNIT_MODULE(gmmu_gk20a_fusa, mm_gmmu_gk20a_fusa_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/gmmu-gk20a-fusa.h b/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/gmmu-gk20a-fusa.h new file mode 100644 index 000000000..8c5fe7f8f --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/gmmu-gk20a-fusa.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef UNIT_MM_HAL_GMMU_GMMU_GK20A_FUSA_H +#define UNIT_MM_HAL_GMMU_GMMU_GK20A_FUSA_H + +struct gk20a; +struct unit_module; + +/** @addtogroup SWUTS-mm-hal-gmmu-gmmu_gk20a_fusa + * @{ + * + * Software Unit Test Specification for mm.hal.gmmu.gmmu_gk20a_fusa + */ + +/** + * Test specification for: test_gk20a_get_pde_pgsz + * + * Description: Test PDE page size + * + * Test Type: Feature based + * + * Targets: gk20a_get_pde_pgsz + * + * Input: test_env_init + * + * Steps: + * - Check PDE page size value using the get_pgsz API + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gk20a_get_pde_pgsz(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_gk20a_get_pte_pgsz + * + * Description: Test PTE page size + * + * Test Type: Feature based + * + * Targets: gk20a_get_pte_pgsz + * + * Input: test_env_init + * + * Steps: + * - Check PTE page size value using the get_pgsz API + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gk20a_get_pte_pgsz(struct unit_module *m, struct gk20a *g, void *args); + +/** @} */ +#endif /* UNIT_MM_HAL_GMMU_GMMU_GK20A_FUSA_H */ diff --git a/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile b/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile new file mode 100644 index 000000000..913706406 --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile @@ -0,0 +1,26 @@ +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = gmmu-gm20b-fusa.o +MODULE = gmmu-gm20b-fusa + +include ../../../../Makefile.units diff --git a/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile.interface.tmk b/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile.interface.tmk new file mode 100644 index 000000000..f617d037a --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=gmmu-gm20b-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile.tmk b/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile.tmk new file mode 100644 index 000000000..47d873d88 --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=gmmu-gm20b-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/gmmu-gm20b-fusa.c b/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/gmmu-gm20b-fusa.c new file mode 100644 index 000000000..1b421c137 --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/gmmu-gm20b-fusa.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include +#include + +#include "hal/mm/gmmu/gmmu_gm20b.h" + +#include "gmmu-gm20b-fusa.h" + + +int test_gm20b_mm_get_big_page_sizes(struct unit_module *m, struct gk20a *g, + void *args) +{ + u32 ret_pgsz; + int ret = UNIT_FAIL; + + ret_pgsz = gm20b_mm_get_big_page_sizes(); + unit_assert(ret_pgsz == (SZ_64K | SZ_128K), goto done); + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s pde_pgsz != GMMU_PAGE_SIZE_SMALL as expected\n", + __func__); + } + + return ret; +} + +struct unit_module_test mm_gmmu_gm20b_fusa_tests[] = { + UNIT_TEST(get_big_pgsz, test_gm20b_mm_get_big_page_sizes, NULL, 0), +}; + +UNIT_MODULE(gmmu_gm20b_fusa, mm_gmmu_gm20b_fusa_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/gmmu-gm20b-fusa.h b/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/gmmu-gm20b-fusa.h new file mode 100644 index 000000000..18cfb3eb9 --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/gmmu-gm20b-fusa.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef UNIT_MM_HAL_GMMU_GMMU_GM20B_FUSA_H +#define UNIT_MM_HAL_GMMU_GMMU_GM20B_FUSA_H + +struct gk20a; +struct unit_module; + +/** @addtogroup SWUTS-mm-hal-gmmu-gmmu_gm20b_fusa + * @{ + * + * Software Unit Test Specification for mm.hal.gmmu.gmmu_gm20b_fusa + */ + +/** + * Test specification for: test_gm20b_mm_get_big_page_sizes + * + * Description: Test big page size + * + * Test Type: Feature based + * + * Targets: gm20b_mm_get_big_page_sizes + * + * Input: test_env_init + * + * Steps: + * - Check big page size value + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gm20b_mm_get_big_page_sizes(struct unit_module *m, struct gk20a *g, + void *args); + +/** @} */ +#endif /* UNIT_MM_HAL_GMMU_GMMU_GM20B_FUSA_H */ diff --git a/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile new file mode 100644 index 000000000..f5f198049 --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile @@ -0,0 +1,26 @@ +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = gmmu-gp10b-fusa.o +MODULE = gmmu-gp10b-fusa + +include ../../../../Makefile.units diff --git a/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile.interface.tmk b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile.interface.tmk new file mode 100644 index 000000000..28a082b6c --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=gmmu-gp10b-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile.tmk b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile.tmk new file mode 100644 index 000000000..7c03db8d1 --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=gmmu-gp10b-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.c b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.c new file mode 100644 index 000000000..f79332dff --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.c @@ -0,0 +1,551 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "hal/mm/gmmu/gmmu_gp10b.h" + +#include "gmmu-gp10b-fusa.h" + +static u32 max_page_table_levels; +static const struct gk20a_mmu_level *mmu_level; + +int test_gp10b_mm_get_default_big_page_size(struct unit_module *m, + struct gk20a *g, void *args) +{ + u32 ret_pgsz; + int ret = UNIT_FAIL; + + ret_pgsz = gp10b_mm_get_default_big_page_size(); + unit_assert(ret_pgsz == U32(SZ_64K), goto done); + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: big page size != 64K as expected\n", __func__); + } + + return ret; +} + +int test_gp10b_mm_get_iommu_bit(struct unit_module *m, + struct gk20a *g, void *args) +{ + u32 ret_bit; + int ret = UNIT_FAIL; + + ret_bit = gp10b_mm_get_iommu_bit(g); + unit_assert(ret_bit == 36U, goto done); + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: iommu bit != 36 as expected\n", __func__); + } + + return ret; +} + +int test_gp10b_get_max_page_table_levels(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + + max_page_table_levels = gp10b_get_max_page_table_levels(g); + unit_assert(max_page_table_levels == 5U, goto done); + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: max page table levels != 5 as expected\n", + __func__); + } + + return ret; +} + +int test_gp10b_mm_get_mmu_levels(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + const struct gk20a_mmu_level *l; + u32 i; + + l = gp10b_mm_get_mmu_levels(g, SZ_64K); + + for (i = 0; i < max_page_table_levels; i++) { + unit_assert((l->update_entry != NULL), goto done); + l++; + } + unit_assert(l->update_entry == NULL, goto done); + + /* If get mmu_levels is successful, copy mmu_levels for future use */ + mmu_level = gp10b_mm_get_mmu_levels(g, SZ_64K); + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: max page table levels != 5 as expected\n", + __func__); + } + + return ret; +} + +int test_update_gmmu_pde3_locked(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + int err; + struct vm_gk20a vm; + struct nvgpu_gmmu_pd pd; + struct nvgpu_gmmu_attrs attrs; + const struct gk20a_mmu_level *l = mmu_level; + u64 vaddr, size = SZ_4K; + u32 data = 0U; + u32 *data_ptr = NULL; + + unit_assert(l != NULL, goto done); + + unit_assert(g->mm.pd_cache == NULL, goto done); + + vm.mm = &g->mm; + err = nvgpu_pd_cache_init(g); + unit_assert(err == 0, goto done); + + err = nvgpu_pd_alloc(&vm, &pd, size); + unit_assert(err == 0, goto done); + + vaddr = nvgpu_pd_gpu_addr(g, &pd); + unit_assert(vaddr != 0ULL, goto done); + + pd.entries = (struct nvgpu_gmmu_pd *) nvgpu_kzalloc(g, + sizeof(struct nvgpu_gmmu_pd)); + unit_assert(pd.entries != NULL, goto done); + + pd.entries->mem = (struct nvgpu_mem *) nvgpu_kzalloc(g, + sizeof(struct nvgpu_mem)); + unit_assert(pd.entries->mem != NULL, goto done); + + nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true); + pd.entries->mem->aperture = APERTURE_SYSMEM; + + l[0].update_entry(&vm, l, &pd, 0U, vaddr, size, &attrs); + + /* Compute data written to pd->mem */ + /* pd.entries->mem is SYSMEM with HONORS_APERTURE */ + data_ptr = pd.mem->cpu_va; + + data |= gmmu_new_pde_aperture_sys_mem_ncoh_f(); + data |= gmmu_new_pde_address_sys_f(size >> + gmmu_new_pde_address_shift_v()); + data |= gmmu_new_pde_vol_true_f(); + + unit_assert(data == data_ptr[0], goto done); + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: failed\n", __func__); + } + if (pd.entries->mem != NULL) { + nvgpu_kfree(g, pd.entries->mem); + } + if (pd.entries != NULL) { + nvgpu_kfree(g, pd.entries); + } + nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false); + nvgpu_pd_free(&vm, &pd); + nvgpu_pd_cache_fini(g); + return ret; +} + +#define F_UPDATE_GMMU_PDE0_SMALL_PAGE 0ULL +#define F_UPDATE_GMMU_PDE0_BIG_PAGE 1ULL + +static const char *f_gmmu_pde0_locked[] = { + "gmmu_small_page_size", + "gmmu_big_page_size", +}; + +int test_update_gmmu_pde0_locked(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + int err; + u64 branch = (u64)args; + struct vm_gk20a vm; + struct nvgpu_gmmu_pd pd; + struct nvgpu_gmmu_attrs attrs; + const struct gk20a_mmu_level *l = mmu_level; + u64 vaddr, size = SZ_4K; + u32 data = 0U; + u32 *data_ptr = NULL; + + unit_assert(l != NULL, goto done); + + unit_assert(g->mm.pd_cache == NULL, goto done); + + vm.mm = &g->mm; + err = nvgpu_pd_cache_init(g); + unit_assert(err == 0, goto done); + + err = nvgpu_pd_alloc(&vm, &pd, size); + unit_assert(err == 0, goto done); + + vaddr = nvgpu_pd_gpu_addr(g, &pd); + unit_assert(vaddr != 0ULL, goto done); + + pd.entries = (struct nvgpu_gmmu_pd *) nvgpu_kzalloc(g, + sizeof(struct nvgpu_gmmu_pd)); + unit_assert(pd.entries != NULL, goto done); + + pd.entries->mem = (struct nvgpu_mem *) nvgpu_kzalloc(g, + sizeof(struct nvgpu_mem)); + unit_assert(pd.entries->mem != NULL, goto done); + + nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true); + pd.entries->mem->aperture = APERTURE_SYSMEM; + attrs.pgsz = branch == F_UPDATE_GMMU_PDE0_SMALL_PAGE ? + GMMU_PAGE_SIZE_SMALL : GMMU_PAGE_SIZE_BIG; + + l[3].update_entry(&vm, l, &pd, 0U, vaddr, size, &attrs); + + /* Compute data written to pd->mem */ + /* pd.entries->mem is SYSMEM with HONORS_APERTURE */ + data_ptr = pd.mem->cpu_va; + + if (branch == F_UPDATE_GMMU_PDE0_SMALL_PAGE) { + data |= gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(); + data |= gmmu_new_dual_pde_address_small_sys_f(size >> + gmmu_new_dual_pde_address_shift_v()); + data |= gmmu_new_dual_pde_vol_small_true_f(); + + unit_assert(data == data_ptr[2], goto done); + } else { + data |= gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(); + data |= gmmu_new_dual_pde_address_big_sys_f(size >> + gmmu_new_dual_pde_address_big_shift_v()); + data |= gmmu_new_dual_pde_vol_big_true_f(); + + unit_assert(data == data_ptr[0], goto done); + } + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: %s failed\n", __func__, + f_gmmu_pde0_locked[branch]); + } + if (pd.entries->mem != NULL) { + nvgpu_kfree(g, pd.entries->mem); + } + if (pd.entries != NULL) { + nvgpu_kfree(g, pd.entries); + } + nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false); + nvgpu_pd_free(&vm, &pd); + nvgpu_pd_cache_fini(g); + return ret; +} + +#define F_ATTRS_PRIV 0x1ULL +#define F_ATTRS_READ_ONLY 0x2ULL +#define F_ATTRS_VALID 0x4ULL +#define F_ATTRS_CACHEABLE 0x8ULL +#define F_ATTRS_APERTURE_VIDMEM 0x10ULL +#define F_PLATFORM_ATOMIC 0x20ULL +#define F_UPDATE_PTE 0x40ULL +#define F_UPDATE_PTE_SPARSE 0x80ULL + +#define F_UPDATE_PTE_PHYS_ADDR_ZERO 0x00ULL +/* F_UPDATE_PTE */ +#define F_UPDATE_PTE_DEFAULT 0x40ULL +/* F_UPDATE_PTE | F_ATTRS_PRIV | F_ATTRS_READ_ONLY */ +#define F_UPDATE_PTE_ATTRS_PRIV_READ_ONLY 0x43ULL +/* F_UPDATE_PTE | F_ATTRS_VALID */ +#define F_UPDATE_PTE_ATTRS_VALID 0x44ULL +/* F_UPDATE_PTE | F_ATTRS_CACHEABLE */ +#define F_UPDATE_PTE_ATTRS_CACHEABLE 0x48ULL +/* F_UPDATE_PTE | F_ATTRS_APERTURE_VIDMEM */ +#define F_UPDATE_PTE_ATTRS_VIDMEM 0x50ULL +/* F_UPDATE_PTE | F_PLATFORM_ATOMIC */ +#define F_UPDATE_PTE_PLATFORM_ATOMIC 0x60ULL + +static const char *f_gmmu_pte_locked[] = { + [F_UPDATE_PTE_DEFAULT] = "update_pte_default", + [F_UPDATE_PTE_ATTRS_PRIV_READ_ONLY] = "update_pte_attrs_priv_read_only", + [F_UPDATE_PTE_ATTRS_VALID] = "update_pte_attrs_valid", + [F_UPDATE_PTE_ATTRS_CACHEABLE] = "update_pte_attrs_cacheable", + [F_UPDATE_PTE_ATTRS_VIDMEM] = "update_pte_attrs_vidmem", + [F_UPDATE_PTE_PLATFORM_ATOMIC] = "update_pte_platform_atomic", + [F_UPDATE_PTE_SPARSE] = "update_pte_sparse", +}; + +int test_update_gmmu_pte_locked(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + int err; + u64 branch = (u64)args; + struct vm_gk20a vm; + struct nvgpu_gmmu_pd pd; + struct nvgpu_gmmu_attrs attrs = {0}; + const struct gk20a_mmu_level *l = mmu_level; + u64 vaddr, size = SZ_4K, paddr = 0; + u32 data = 0U; + u32 *data_ptr = NULL; + + unit_assert(l != NULL, goto done); + + unit_assert(g->mm.pd_cache == NULL, goto done); + + vm.mm = &g->mm; + err = nvgpu_pd_cache_init(g); + unit_assert(err == 0, goto done); + + err = nvgpu_pd_alloc(&vm, &pd, size); + unit_assert(err == 0, goto done); + + vaddr = nvgpu_pd_gpu_addr(g, &pd); + unit_assert(vaddr != 0ULL, goto done); + + pd.entries = (struct nvgpu_gmmu_pd *) nvgpu_kzalloc(g, + sizeof(struct nvgpu_gmmu_pd)); + unit_assert(pd.entries != NULL, goto done); + + pd.entries->mem = (struct nvgpu_mem *) nvgpu_kzalloc(g, + sizeof(struct nvgpu_mem)); + unit_assert(pd.entries->mem != NULL, goto done); + + nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true); + pd.entries->mem->aperture = APERTURE_SYSMEM; + attrs.pgsz = GMMU_PAGE_SIZE_SMALL; + vm.gmmu_page_sizes[GMMU_PAGE_SIZE_SMALL] = SZ_4K; + + paddr = branch & F_UPDATE_PTE ? size : 0ULL; + nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, + (branch & F_PLATFORM_ATOMIC ? true : false)); + + attrs.platform_atomic = branch & F_PLATFORM_ATOMIC ? true : false; + attrs.aperture = branch & F_ATTRS_APERTURE_VIDMEM ? + APERTURE_VIDMEM : APERTURE_SYSMEM; + attrs.priv = branch & F_ATTRS_PRIV ? true : false; + attrs.rw_flag = branch & F_ATTRS_READ_ONLY ? + gk20a_mem_flag_read_only : gk20a_mem_flag_none; + attrs.valid = branch & F_ATTRS_VALID ? true : false; + attrs.cacheable = branch & F_ATTRS_CACHEABLE ? true : false; + attrs.sparse = branch & F_UPDATE_PTE_SPARSE ? true : false; + + l[4].update_entry(&vm, l, &pd, 0U, vaddr, paddr, &attrs); + + /* Compute data written to pd->mem */ + /* pd.entries->mem is SYSMEM with HONORS_APERTURE */ + data_ptr = pd.mem->cpu_va; + + if (branch & F_UPDATE_PTE) { + data |= branch & F_ATTRS_APERTURE_VIDMEM ? + gmmu_new_pte_address_vid_f(paddr >> + gmmu_new_pte_address_shift_v()) : + gmmu_new_pte_address_sys_f(paddr >> + gmmu_new_pte_address_shift_v()); + data |= branch & F_PLATFORM_ATOMIC ? + gmmu_new_pte_aperture_sys_mem_coh_f() : + branch & F_ATTRS_APERTURE_VIDMEM ? + gmmu_new_pte_aperture_video_memory_f() : + gmmu_new_pte_aperture_sys_mem_ncoh_f(); + data |= branch & F_ATTRS_VALID ? gmmu_new_pte_valid_true_f() : + gmmu_new_pte_valid_false_f(); + data |= branch & F_ATTRS_PRIV ? + gmmu_new_pte_privilege_true_f() : 0U; + data |= branch & F_ATTRS_READ_ONLY ? + gmmu_new_pte_read_only_true_f() : 0U; + + if (!(branch & F_ATTRS_CACHEABLE)) { + data |= branch & F_ATTRS_VALID ? + gmmu_new_pte_vol_true_f() : + gmmu_new_pte_read_only_true_f(); + } + } else if (branch & F_UPDATE_PTE_SPARSE) { + data = gmmu_new_pte_valid_false_f(); + data |= gmmu_new_pte_vol_true_f(); + } + + unit_assert(data == data_ptr[0], goto done); + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: %s failed\n", __func__, + f_gmmu_pte_locked[branch]); + } + if (pd.entries->mem != NULL) { + nvgpu_kfree(g, pd.entries->mem); + } + if (pd.entries != NULL) { + nvgpu_kfree(g, pd.entries); + } + nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false); + nvgpu_pd_free(&vm, &pd); + nvgpu_pd_cache_fini(g); + return ret; +} + +#define F_PDE_V0_VALUE_SET 0x1ULL +#define F_PDE_V1_VALUE_SET 0x2ULL +#define F_PDE_V2_VALUE_SET 0x4ULL +#define F_PDE_V3_VALUE_SET 0x8ULL + +#define F_PDE_BIG_PAGE_APERTURE_SET_ONLY 0x01ULL +#define F_PDE_BIG_PAGE_APERTURE_ADDR_SET 0x03ULL +#define F_PDE_SMALL_PAGE_APERTURE_SET_ONLY 0x04ULL +#define F_PDE_SMALL_PAGE_APERTURE_ADDR_SET 0x0CULL +#define F_PDE_SMALL_BIG_SET 0x0FULL +#define F_PDE0_PGSZ_MEM_NULL 0x10ULL + +static const char *f_get_pde0_pgsz[] = { + [F_PDE_BIG_PAGE_APERTURE_SET_ONLY] = + "get_pde0_pgsz_big_page_only_aperture_set", + [F_PDE_BIG_PAGE_APERTURE_ADDR_SET] = + "get_pde0_pgsz_big_page_aperture_addr_set", + [F_PDE_SMALL_PAGE_APERTURE_SET_ONLY] = + "get_pde0_pgsz_small_page_only_aperture_set", + [F_PDE_SMALL_PAGE_APERTURE_ADDR_SET] = + "get_pde0_pgsz_small_page_aperture_addr_set", + [F_PDE_SMALL_BIG_SET] = "get_pde0_pgsz_small_big_set", + [F_PDE0_PGSZ_MEM_NULL] = "get_pde0_pgsz_mem_null", +}; + +int test_gp10b_get_pde0_pgsz(struct unit_module *m, struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + int err; + u64 branch = (u64)args; + struct vm_gk20a vm; + struct nvgpu_gmmu_pd pd; + const struct gk20a_mmu_level *l = mmu_level; + u64 vaddr, size = SZ_4K; + u32 *data; + u32 ret_pgsz; + struct nvgpu_mem *tmp_mem_ptr = NULL; + + unit_assert(l != NULL, goto done); + + unit_assert(g->mm.pd_cache == NULL, goto done); + + vm.mm = &g->mm; + err = nvgpu_pd_cache_init(g); + unit_assert(err == 0, goto done); + + err = nvgpu_pd_alloc(&vm, &pd, size); + unit_assert(err == 0, goto done); + + vaddr = nvgpu_pd_gpu_addr(g, &pd); + unit_assert(vaddr != 0ULL, goto done); + + if (branch & F_PDE0_PGSZ_MEM_NULL) { + tmp_mem_ptr = pd.mem; + pd.mem = NULL; + } else { + data = pd.mem->cpu_va; + + data[0] = branch & F_PDE_V0_VALUE_SET ? + (gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() | + gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() | + gmmu_new_dual_pde_aperture_big_video_memory_f()) : 0U; + data[1] = branch & F_PDE_V1_VALUE_SET ? 1U : 0U; + data[2] = branch & F_PDE_V2_VALUE_SET ? + (gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() | + gmmu_new_dual_pde_aperture_small_sys_mem_coh_f() | + gmmu_new_dual_pde_aperture_small_video_memory_f()) : 0U; + data[3] = branch & F_PDE_V3_VALUE_SET ? 1U : 0U; + } + + ret_pgsz = l[3].get_pgsz(g, l, &pd, 0U); + + if (branch == F_PDE_BIG_PAGE_APERTURE_ADDR_SET) { + unit_assert(ret_pgsz == GMMU_PAGE_SIZE_BIG, goto done); + } else if (branch == F_PDE_SMALL_PAGE_APERTURE_ADDR_SET) { + unit_assert(ret_pgsz == GMMU_PAGE_SIZE_SMALL, goto done); + } else { + unit_assert(ret_pgsz == GMMU_NR_PAGE_SIZES, goto done); + } + + if (branch & F_PDE0_PGSZ_MEM_NULL) { + pd.mem = tmp_mem_ptr; + } + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s: %s failed\n", __func__, + f_get_pde0_pgsz[branch]); + } + nvgpu_pd_free(&vm, &pd); + nvgpu_pd_cache_fini(g); + return ret; +} + +struct unit_module_test mm_gmmu_gp10b_fusa_tests[] = { + UNIT_TEST(big_pgsz, test_gp10b_mm_get_default_big_page_size, NULL, 0), + UNIT_TEST(iommu_bit, test_gp10b_mm_get_iommu_bit, NULL, 0), + UNIT_TEST(max_page_table_levels, test_gp10b_get_max_page_table_levels, NULL, 0), + UNIT_TEST(mmu_levels, test_gp10b_mm_get_mmu_levels, NULL, 0), + UNIT_TEST(update_gmmu_pde3_locked, test_update_gmmu_pde3_locked, NULL, 0), + UNIT_TEST(update_gmmu_pde0_locked_s0, test_update_gmmu_pde0_locked, (void *)F_UPDATE_GMMU_PDE0_SMALL_PAGE, 0), + UNIT_TEST(update_gmmu_pde0_locked_s1, test_update_gmmu_pde0_locked, (void *)F_UPDATE_GMMU_PDE0_BIG_PAGE, 0), + UNIT_TEST(update_gmmu_pte_locked_s0, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_PHYS_ADDR_ZERO, 0), + UNIT_TEST(update_gmmu_pte_locked_s1, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_DEFAULT, 0), + UNIT_TEST(update_gmmu_pte_locked_s2, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_PRIV_READ_ONLY, 0), + UNIT_TEST(update_gmmu_pte_locked_s3, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_VALID, 0), + UNIT_TEST(update_gmmu_pte_locked_s4, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_CACHEABLE, 0), + UNIT_TEST(update_gmmu_pte_locked_s5, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_VIDMEM, 0), + UNIT_TEST(update_gmmu_pte_locked_s6, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_PLATFORM_ATOMIC, 0), + UNIT_TEST(update_gmmu_pte_locked_s7, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_SPARSE, 0), + UNIT_TEST(gp10b_get_pde0_pgsz_s0, test_gp10b_get_pde0_pgsz, (void *)F_PDE_BIG_PAGE_APERTURE_SET_ONLY, 0), + UNIT_TEST(gp10b_get_pde0_pgsz_s1, test_gp10b_get_pde0_pgsz, (void *)F_PDE_BIG_PAGE_APERTURE_ADDR_SET, 0), + UNIT_TEST(gp10b_get_pde0_pgsz_s2, test_gp10b_get_pde0_pgsz, (void *)F_PDE_SMALL_PAGE_APERTURE_SET_ONLY, 0), + UNIT_TEST(gp10b_get_pde0_pgsz_s3, test_gp10b_get_pde0_pgsz, (void *)F_PDE_SMALL_PAGE_APERTURE_ADDR_SET, 0), + UNIT_TEST(gp10b_get_pde0_pgsz_s4, test_gp10b_get_pde0_pgsz, (void *)F_PDE_SMALL_BIG_SET, 0), + UNIT_TEST(gp10b_get_pde0_pgsz_s5, test_gp10b_get_pde0_pgsz, (void *)F_PDE0_PGSZ_MEM_NULL, 0), +}; + +UNIT_MODULE(gmmu_gp10b_fusa, mm_gmmu_gp10b_fusa_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.h b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.h new file mode 100644 index 000000000..c6da4760d --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef UNIT_MM_HAL_GMMU_GMMU_GP10B_FUSA_H +#define UNIT_MM_HAL_GMMU_GMMU_GP10B_FUSA_H + +struct gk20a; +struct unit_module; + +/** @addtogroup SWUTS-mm-hal-gmmu-gmmu_gp10b_fusa + * @{ + * + * Software Unit Test Specification for mm.hal.gmmu.gmmu_gp10b_fusa + */ + +/** + * Test specification for: test_gp10b_mm_get_default_big_page_size + * + * Description: Test big page size + * + * Test Type: Feature based + * + * Targets: gp10b_mm_get_default_big_page_size + * + * Input: None + * + * Steps: + * - Check big page size value and confirm that size is 64K. + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gp10b_mm_get_default_big_page_size(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gp10b_mm_get_iommu_bit + * + * Description: Test IOMMU bit number + * + * Test Type: Feature based + * + * Targets: gp10b_mm_get_iommu_bit + * + * Input: None + * + * Steps: + * - Check iommu bit is equal to 36. + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gp10b_mm_get_iommu_bit(struct unit_module *m, struct gk20a *g, + void *args); + +/** + * Test specification for: test_gp10b_get_max_page_table_levels + * + * Description: Test max page table levels + * + * Test Type: Feature based + * + * Targets: gp10b_get_max_page_table_levels + * + * Input: None + * + * Steps: + * - Check max page table levels is 5. + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gp10b_get_max_page_table_levels(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gp10b_mm_get_mmu_levels + * + * Description: Test mmu_levels structure + * + * Test Type: Feature based + * + * Targets: gp10b_mm_get_mmu_levels + * + * Input: None + * + * Steps: + * - Copy mmu_levels structure and validate struct using update_entry pointer. + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gp10b_mm_get_mmu_levels(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_update_gmmu_pde3_locked + * + * Description: Test mmu_levels update entry function + * + * Test Type: Feature based + * + * Targets: update_gmmu_pde3_locked, pte_dbg_print + * + * Input: None + * + * Steps: + * - Update gmmu pde3 for given physical address. + * - Check if data written to memory is as expected. + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_update_gmmu_pde3_locked(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_update_gmmu_pde0_locked + * + * Description: Test mmu_level 3 update entry function + * + * Test Type: Feature based + * + * Targets: update_gmmu_pde0_locked, pte_dbg_print + * + * Input: args (value can be F_UPDATE_GMMU_PDE0_SMALL_PAGE or + * F_UPDATE_GMMU_PDE0_BIG_PAGE) + * + * Steps: + * - Update gmmu pde3 for given physical address. + * - For big and small page size, check data written to memory. + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_update_gmmu_pde0_locked(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_update_gmmu_pte_locked + * + * Description: Test mmu_level 4 update entry function + * + * Test Type: Feature based + * + * Targets: update_gmmu_pte_locked, update_pte, update_pte_sparse, + * gmmu_aperture_mask + * + * Input: args (value can be F_UPDATE_PTE_PHYS_ADDR_ZERO, F_UPDATE_PTE_DEFAULT, + * F_UPDATE_PTE_ATTRS_PRIV_READ_ONLY, F_UPDATE_PTE_ATTRS_VALID, + * F_UPDATE_PTE_ATTRS_CACHEABLE, F_UPDATE_PTE_ATTRS_VIDMEM, + * F_UPDATE_PTE_PLATFORM_ATOMIC or F_UPDATE_PTE_SPARSE) + * + * Steps: + * - Update gmmu pte for given physical address. + * - Check data written to pd mem for various scenarios such as cacheable GMMU + * mapping, priviledged mapping, read only address, etc. + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_update_gmmu_pte_locked(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gp10b_get_pde0_pgsz + * + * Description: Test GMMU level 3 page size function + * + * Test Type: Feature based + * + * Targets: gp10b_get_pde0_pgsz + * + * Input: args (value can be F_PDE_BIG_PAGE_APERTURE_SET_ONLY, + * F_PDE_BIG_PAGE_APERTURE_ADDR_SET, F_PDE_SMALL_PAGE_APERTURE_SET_ONLY, + * F_PDE_SMALL_PAGE_APERTURE_ADDR_SET, F_PDE_SMALL_BIG_SET or + * F_PDE0_PGSZ_MEM_NULL) + * + * Steps: + * - Check pde0 page size for given aperture values + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gp10b_get_pde0_pgsz(struct unit_module *m, struct gk20a *g, + void *args); + +/** @} */ +#endif /* UNIT_MM_HAL_GMMU_GMMU_GP10B_FUSA_H */ diff --git a/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile b/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile new file mode 100644 index 000000000..ac61b2b2e --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile @@ -0,0 +1,26 @@ +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = gmmu-gv11b-fusa.o +MODULE = gmmu-gv11b-fusa + +include ../../../../Makefile.units diff --git a/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile.interface.tmk b/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile.interface.tmk new file mode 100644 index 000000000..035c336d1 --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=gmmu-gv11b-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile.tmk b/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile.tmk new file mode 100644 index 000000000..ef2ee5fde --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=gmmu-gv11b-fusa + +include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/gmmu-gv11b-fusa.c b/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/gmmu-gv11b-fusa.c new file mode 100644 index 000000000..96c5a9f9b --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/gmmu-gv11b-fusa.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include + +#include +#include +#include + +#include "hal/mm/gmmu/gmmu_gv11b.h" + +#include "gmmu-gv11b-fusa.h" + +#define F_GV11B_GPU_PHYS_ADDR_GMMU_ATTRS_NULL 0 +#define F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_FALSE 1 +#define F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_TRUE 2 + +/* defined in gmmu_gv11b_fusa.c */ +#define NVGPU_L3_ALLOC_BIT BIT64(36) + +int test_gv11b_gpu_phys_addr(struct unit_module *m, struct gk20a *g, void *args) +{ + struct nvgpu_gmmu_attrs attrs = {0}; + struct nvgpu_gmmu_attrs *attrs_ptr; + u64 phys = BIT(10); + u64 ret_phys; + u64 branch = (u64)args; + int ret = UNIT_FAIL; + + attrs_ptr = branch == F_GV11B_GPU_PHYS_ADDR_GMMU_ATTRS_NULL ? + NULL : &attrs; + + attrs.l3_alloc = branch == F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_FALSE ? + false : true; + + ret_phys = gv11b_gpu_phys_addr(g, attrs_ptr, phys); + + if (branch == F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_TRUE) { + unit_assert(ret_phys == (phys | NVGPU_L3_ALLOC_BIT), goto done); + } else { + unit_assert(ret_phys == phys, goto done); + } + + ret = UNIT_SUCCESS; + +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s pde_pgsz != GMMU_PAGE_SIZE_SMALL as expected\n", + __func__); + } + + return ret; +} + +struct unit_module_test mm_gmmu_gv11b_fusa_tests[] = { + UNIT_TEST(gpu_phys_addr_s0, test_gv11b_gpu_phys_addr, (void *)F_GV11B_GPU_PHYS_ADDR_GMMU_ATTRS_NULL, 0), + UNIT_TEST(gpu_phys_addr_s1, test_gv11b_gpu_phys_addr, (void *)F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_FALSE, 0), + UNIT_TEST(gpu_phys_addr_s2, test_gv11b_gpu_phys_addr, (void *)F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_TRUE, 0), +}; + +UNIT_MODULE(gmmu_gv11b_fusa, mm_gmmu_gv11b_fusa_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/gmmu-gv11b-fusa.h b/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/gmmu-gv11b-fusa.h new file mode 100644 index 000000000..fff8d987f --- /dev/null +++ b/userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/gmmu-gv11b-fusa.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef UNIT_MM_HAL_GMMU_GMMU_GV11B_FUSA_H +#define UNIT_MM_HAL_GMMU_GMMU_GV11B_FUSA_H + +struct gk20a; +struct unit_module; + +/** @addtogroup SWUTS-mm-hal-gmmu-gmmu_gv11b_fusa + * @{ + * + * Software Unit Test Specification for mm.hal.gmmu.gmmu_gv11b_fusa + */ + +/** + * Test specification for: test_gv11b_gpu_phys_addr + * + * Description: Test PTE page size + * + * Test Type: Feature based + * + * Targets: gk20a_get_pte_pgsz + * + * Input: args (value can be F_GV11B_GPU_PHYS_ADDR_GMMU_ATTRS_NULL, + * F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_FALSE or + * F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_TRUE) + * + * Steps: + * - Check PTE page size value using the get_pgsz API + * + * Output: Returns SUCCESS if the steps above were executed successfully. FAIL + * otherwise. + */ +int test_gv11b_gpu_phys_addr(struct unit_module *m, struct gk20a *g, + void *args); + +/** @} */ +#endif /* UNIT_MM_HAL_GMMU_GMMU_GV11B_FUSA_H */