diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 1a04c11a4..b14d97023 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -172,6 +172,7 @@ nvgpu-y += \ hal/bus/bus_gp10b.o \ hal/bus/bus_gv100.o \ hal/bus/bus_tu104.o \ + hal/gr/init/gr_init_gm20b.o \ hal/gr/hwpm_map/hwpm_map_gv100.o \ hal/priv_ring/priv_ring_gm20b.o \ hal/priv_ring/priv_ring_gp10b.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 936846a70..7c50c406e 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -336,6 +336,7 @@ srcs += common/sim.c \ hal/bus/bus_gp10b.c \ hal/bus/bus_gv100.c \ hal/bus/bus_tu104.c \ + hal/gr/init/gr_init_gm20b.c \ hal/gr/hwpm_map/hwpm_map_gv100.c \ hal/priv_ring/priv_ring_gm20b.c \ hal/priv_ring/priv_ring_gp10b.c \ diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 340b5a87e..fc117eaef 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -68,8 +68,6 @@ #include #define BLK_SIZE (256U) -#define FE_PWR_MODE_TIMEOUT_MAX 2000U -#define FE_PWR_MODE_TIMEOUT_DEFAULT 10U #define CTXSW_MEM_SCRUBBING_TIMEOUT_MAX 1000U #define CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT 10U #define FECS_ARB_CMD_TIMEOUT_MAX 40 @@ -1228,26 +1226,12 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g, if (gr->ctx_vars.golden_image_initialized) { goto clean_up; } - if (!nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - struct nvgpu_timeout timeout; - nvgpu_timeout_init(g, &timeout, - FE_PWR_MODE_TIMEOUT_MAX / - FE_PWR_MODE_TIMEOUT_DEFAULT, - NVGPU_TIMER_RETRY_TIMER); - gk20a_writel(g, gr_fe_pwr_mode_r(), - gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_force_on_f()); - do { - u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); - if (req == gr_fe_pwr_mode_req_done_v()) { - break; - } - nvgpu_udelay(FE_PWR_MODE_TIMEOUT_DEFAULT); - } while (nvgpu_timeout_expired_msg(&timeout, - "timeout forcing FE on") == 0); + err = g->ops.gr.init.fe_pwr_mode_force_on(g, true); + if (err != 0) { + goto clean_up; } - gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(), gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() | gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() | @@ -1274,24 +1258,9 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g, (void) gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); nvgpu_udelay(10); - if (!nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - struct nvgpu_timeout timeout; - - nvgpu_timeout_init(g, &timeout, - FE_PWR_MODE_TIMEOUT_MAX / - FE_PWR_MODE_TIMEOUT_DEFAULT, - NVGPU_TIMER_RETRY_TIMER); - gk20a_writel(g, gr_fe_pwr_mode_r(), - gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_auto_f()); - - do { - u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); - if (req == gr_fe_pwr_mode_req_done_v()) { - break; - } - nvgpu_udelay(FE_PWR_MODE_TIMEOUT_DEFAULT); - } while (nvgpu_timeout_expired_msg(&timeout, - "timeout setting FE power to auto") == 0); + err = g->ops.gr.init.fe_pwr_mode_force_on(g, false); + if (err != 0) { + goto clean_up; } /* clear scc ram */ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index a74c1feff..bdfb16bb1 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -44,6 +44,7 @@ #include "hal/cbc/cbc_gm20b.h" #include "hal/fuse/fuse_gm20b.h" #include "hal/fifo/engines_gm20b.h" +#include "hal/gr/init/gr_init_gm20b.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -421,7 +422,11 @@ static const struct gpu_ops gm20b_ops = { .add_stencil = NULL, .get_gpcs_swdx_dss_zbc_c_format_reg = NULL, .get_gpcs_swdx_dss_zbc_z_format_reg = NULL, - } + }, + .init = { + .fe_pwr_mode_force_on = + gm20b_gr_init_fe_pwr_mode_force_on, + }, }, .fb = { .init_hw = gm20b_fb_init_hw, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 2a8d3c672..3ba80fa61 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -50,6 +50,7 @@ #include "hal/fuse/fuse_gm20b.h" #include "hal/fuse/fuse_gp10b.h" #include "hal/fifo/engines_gm20b.h" +#include "hal/gr/init/gr_init_gm20b.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -470,7 +471,11 @@ static const struct gpu_ops gp10b_ops = { gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg, .get_gpcs_swdx_dss_zbc_z_format_reg = gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg, - } + }, + .init = { + .fe_pwr_mode_force_on = + gm20b_gr_init_fe_pwr_mode_force_on, + }, }, .fb = { .init_hw = gm20b_fb_init_hw, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index d47732779..880c7a7b5 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -34,6 +34,8 @@ #include "hal/fuse/fuse_gp10b.h" #include "hal/fuse/fuse_gp106.h" #include "hal/fifo/engines_gv11b.h" +#include "hal/gr/init/gr_init_gm20b.h" +#include "hal/gr/hwpm_map/hwpm_map_gv100.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -50,7 +52,6 @@ #include "common/gr/zbc/gr_zbc_gp10b.h" #include "common/gr/zbc/gr_zbc_gv11b.h" #include "common/gr/fecs_trace/fecs_trace_gm20b.h" -#include "hal/gr/hwpm_map/hwpm_map_gv100.h" #include "common/therm/therm_gm20b.h" #include "common/therm/therm_gp106.h" #include "common/therm/therm_gp10b.h" @@ -606,7 +607,11 @@ static const struct gpu_ops gv100_ops = { gv100_gr_hwpm_map_align_regs_perf_pma, .get_active_fbpa_mask = gv100_gr_hwpm_map_get_active_fbpa_mask, - } + }, + .init = { + .fe_pwr_mode_force_on = + gm20b_gr_init_fe_pwr_mode_force_on, + }, }, .fb = { .init_hw = gv11b_fb_init_hw, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e48b152f4..6faa2e35e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -37,6 +37,8 @@ #include "hal/fuse/fuse_gm20b.h" #include "hal/fuse/fuse_gp10b.h" #include "hal/fifo/engines_gv11b.h" +#include "hal/gr/init/gr_init_gm20b.h" +#include "hal/gr/hwpm_map/hwpm_map_gv100.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -51,7 +53,6 @@ #include "common/gr/zbc/gr_zbc_gv11b.h" #include "common/gr/fecs_trace/fecs_trace_gm20b.h" #include "common/gr/fecs_trace/fecs_trace_gv11b.h" -#include "hal/gr/hwpm_map/hwpm_map_gv100.h" #include "common/therm/therm_gm20b.h" #include "common/therm/therm_gp10b.h" #include "common/therm/therm_gv11b.h" @@ -563,7 +564,11 @@ static const struct gpu_ops gv11b_ops = { .hwpm_map = { .align_regs_perf_pma = gv100_gr_hwpm_map_align_regs_perf_pma, - } + }, + .init = { + .fe_pwr_mode_force_on = + gm20b_gr_init_fe_pwr_mode_force_on, + }, }, .fb = { .init_hw = gv11b_fb_init_hw, diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c new file mode 100644 index 000000000..2092b3daf --- /dev/null +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "gr_init_gm20b.h" + +#include + +#define FE_PWR_MODE_TIMEOUT_MAX_US 2000U +#define FE_PWR_MODE_TIMEOUT_DEFAULT_US 10U + +int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on) +{ + struct nvgpu_timeout timeout; + int ret = -ETIMEDOUT; + u32 reg_val; + + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + return 0; + } + + if (force_on) { + reg_val = gr_fe_pwr_mode_req_send_f() | + gr_fe_pwr_mode_mode_force_on_f(); + } else { + reg_val = gr_fe_pwr_mode_req_send_f() | + gr_fe_pwr_mode_mode_auto_f(); + } + + nvgpu_timeout_init(g, &timeout, + FE_PWR_MODE_TIMEOUT_MAX_US / + FE_PWR_MODE_TIMEOUT_DEFAULT_US, + NVGPU_TIMER_RETRY_TIMER); + + nvgpu_writel(g, gr_fe_pwr_mode_r(), reg_val); + + do { + u32 req = gr_fe_pwr_mode_req_v( + nvgpu_readl(g, gr_fe_pwr_mode_r())); + if (req == gr_fe_pwr_mode_req_done_v()) { + ret = 0; + break; + } + + nvgpu_udelay(FE_PWR_MODE_TIMEOUT_DEFAULT_US); + } while (nvgpu_timeout_expired_msg(&timeout, + "timeout setting FE mode %u", force_on) == 0); + + return ret; +} diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h new file mode 100644 index 000000000..3d8e3bda5 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_GR_INIT_GM20B_H +#define NVGPU_GR_INIT_GM20B_H + +#include + +struct gk20a; + +int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on); + +#endif /* NVGPU_GR_INIT_GM20B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 238601524..8692d7bf4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -635,6 +635,11 @@ struct gpu_ops { u32 (*get_active_fbpa_mask)(struct gk20a *g); } hwpm_map; + struct { + int (*fe_pwr_mode_force_on)(struct gk20a *g, + bool force_on); + } init; + u32 (*fecs_falcon_base_addr)(void); u32 (*gpccs_falcon_base_addr)(void); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index a14a36b91..d2ee12f78 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -36,6 +36,8 @@ #include "hal/fuse/fuse_gp10b.h" #include "hal/fuse/fuse_gp106.h" #include "hal/fifo/engines_gv11b.h" +#include "hal/gr/init/gr_init_gm20b.h" +#include "hal/gr/hwpm_map/hwpm_map_gv100.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -54,7 +56,6 @@ #include "common/gr/zbc/gr_zbc_gv11b.h" #include "common/gr/fecs_trace/fecs_trace_gm20b.h" #include "common/gr/fecs_trace/fecs_trace_gv11b.h" -#include "hal/gr/hwpm_map/hwpm_map_gv100.h" #include "common/therm/therm_gm20b.h" #include "common/therm/therm_gp10b.h" #include "common/therm/therm_gp106.h" @@ -632,7 +633,11 @@ static const struct gpu_ops tu104_ops = { gv100_gr_hwpm_map_align_regs_perf_pma, .get_active_fbpa_mask = gv100_gr_hwpm_map_get_active_fbpa_mask, - } + }, + .init = { + .fe_pwr_mode_force_on = + gm20b_gr_init_fe_pwr_mode_force_on, + }, }, .fb = { .init_hw = gv11b_fb_init_hw,