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gpu: nvgpu: fix ltc isr, unit tests
LTC isr doesn't handle ECC errors correctly. INTR3 reports only parity ECC errors and INTR reports SEC/DED ECC errors. nvgpu managed both these errors with same counters. Fix it as per Volta ECC HW Functional Description. JIRA NVGPU-6982 Change-Id: I6ddaab55f7e1354ad9b832672a9006b7e58df9f7 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2605012 (cherry picked from commit 5f92651e921b17cb61bbbb8954128c787cd89238) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2632548 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
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449a4823d4
commit
c463810bcd
@@ -284,12 +284,38 @@ static void nvgpu_init_gr_manager(struct gk20a *g)
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gr_syspipe->num_gpc = 1;
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}
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static int ltc_ecc_init_fault_check(struct unit_module *m, struct gk20a *g,
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unsigned int number)
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{
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struct nvgpu_posix_fault_inj *kmem_fi =
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nvgpu_kmem_get_fault_injection();
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int err;
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/* Re-Init dependent ECC unit */
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err = nvgpu_ecc_init_support(g);
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if (err != 0) {
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unit_err(m, "ecc init failed\n");
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return err;
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}
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nvgpu_posix_enable_fault_injection(kmem_fi, true, number);
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err = g->ops.ltc.ecc_init(g);
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if (err == 0) {
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unit_err(m, "nvgpu_ecc_counter_init_per_lts() failed to return error\n");
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return -1;
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}
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return 0;
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}
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int test_ltc_ecc_init_free(struct unit_module *m, struct gk20a *g, void *args)
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{
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int ret = UNIT_SUCCESS;
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int err;
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struct nvgpu_ecc_stat **save_sec_ptr = g->ecc.ltc.ecc_sec_count;
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struct nvgpu_ecc_stat **save_ded_ptr = g->ecc.ltc.ecc_ded_count;
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struct nvgpu_ecc_stat **save_tstg_ecc_ptr = g->ecc.ltc.tstg_ecc_parity_count;
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struct nvgpu_ecc_stat **save_dstg_ecc_ptr = g->ecc.ltc.dstg_be_ecc_parity_count;
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struct nvgpu_posix_fault_inj *kmem_fi =
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nvgpu_kmem_get_fault_injection();
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@@ -312,14 +338,15 @@ int test_ltc_ecc_init_free(struct unit_module *m, struct gk20a *g, void *args)
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g->ecc.ltc.ecc_sec_count = NULL;
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g->ecc.ltc.ecc_ded_count = NULL;
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g->ecc.ltc.tstg_ecc_parity_count = NULL;
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g->ecc.ltc.dstg_be_ecc_parity_count = NULL;
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/*
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* Call with failure on first kzalloc
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* Call with failure on first kzalloc for sec_ecc_count
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*/
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nvgpu_posix_enable_fault_injection(kmem_fi, true, 0);
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err = g->ops.ltc.ecc_init(g);
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if (err == 0) {
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unit_err(m, "nvgpu_ecc_counter_init_per_lts() failed to return error\n");
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err = ltc_ecc_init_fault_check(m, g, 0);
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if (err) {
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unit_err(m, "sec_ecc_count alloc fault check failed\n");
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ret = UNIT_FAIL;
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goto done;
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}
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@@ -328,28 +355,42 @@ int test_ltc_ecc_init_free(struct unit_module *m, struct gk20a *g, void *args)
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* Call with failure on third kzalloc for the 2nd array dimension and to
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* validate unrolling.
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*/
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nvgpu_posix_enable_fault_injection(kmem_fi, true, 2);
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err = g->ops.ltc.ecc_init(g);
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if (err == 0) {
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unit_err(m, "nvgpu_ecc_counter_init_per_lts() failed to return error\n");
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err = ltc_ecc_init_fault_check(m, g, 2);
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if (err) {
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unit_err(m, "sec_ecc_count alloc for LTC 1 fault check failed\n");
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ret = UNIT_FAIL;
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goto done;
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}
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/* Re-Init dependent ECC unit */
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err = nvgpu_ecc_init_support(g);
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if (err != 0) {
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unit_return_fail(m, "ecc init failed\n");
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/*
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* Call with failure on 4th kzalloc for ded_ecc_count and get more
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* branch/line coverage.
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*/
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err = ltc_ecc_init_fault_check(m, g, 4);
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if (err) {
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unit_err(m, "dec_ecc_count alloc fault check failed\n");
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ret = UNIT_FAIL;
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goto done;
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}
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/*
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* Call with failure on 4th kzalloc for second stat and get more
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* Call with failure on 8th kzalloc for tstg_ecc_parity_count and get more
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* branch/line coverage.
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*/
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nvgpu_posix_enable_fault_injection(kmem_fi, true, 4);
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err = g->ops.ltc.ecc_init(g);
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if (err == 0) {
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unit_err(m, "nvgpu_ecc_counter_init_per_lts() failed to return error\n");
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err = ltc_ecc_init_fault_check(m, g, 8);
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if (err) {
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unit_err(m, "tstg_ecc_parity_count alloc fault check failed\n");
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ret = UNIT_FAIL;
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goto done;
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}
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/*
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* Call with failure on 11th kzalloc for dstg_be_ecc_parity_count and get more
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* branch/line coverage.
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*/
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err = ltc_ecc_init_fault_check(m, g, 11);
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if (err) {
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unit_err(m, "dstg_be_ecc_parity_count alloc fault check failed\n");
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ret = UNIT_FAIL;
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goto done;
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}
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@@ -373,6 +414,8 @@ done:
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nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
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g->ecc.ltc.ecc_sec_count = save_sec_ptr;
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g->ecc.ltc.ecc_ded_count = save_ded_ptr;
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g->ecc.ltc.tstg_ecc_parity_count = save_tstg_ecc_ptr;
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g->ecc.ltc.dstg_be_ecc_parity_count = save_dstg_ecc_ptr;
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nvgpu_gr_free(g);
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return ret;
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@@ -464,105 +507,102 @@ int test_ltc_intr(struct unit_module *m, struct gk20a *g, void *args)
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_LTS(tstg_ecc_parity_count);
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if (err != 0) {
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unit_err(m, "failed to init tstg_ecc_parity_count\n");
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err = UNIT_FAIL;
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_LTS(dstg_be_ecc_parity_count);
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if (err != 0) {
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unit_err(m, "failed to init dstg_be_ecc_parity_count\n");
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err = UNIT_FAIL;
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goto done;
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}
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/* test with no intr pending */
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g->ops.ltc.intr.isr(g, 0);
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/* test with corrected intr, expect BUG */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_corrected_m());
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EXPECT_BUG(g->ops.ltc.intr.isr(g, 0));
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/* test with intr, but no corrected or uncorrected bits */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set corrected & uncorrected overflow bits */
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/* set uncorrected overflow bits */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set corrected & uncorrected overflow bits in second instance */
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/* set uncorrected overflow bits in second instance */
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nvgpu_posix_io_writel_reg_space(g,
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ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset1,
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r() + offset1,
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set corrected overflow bit independently for branch coverage */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set uncorrected overflow bit independently for branch coverage */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/*
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* Clear the corrected & uncorrected overflow bits. And for branch
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* coverage, set the uncorrected & corrected err counts.
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* Clear the uncorrected overflow bits. And for branch
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* coverage, set the uncorrected err count.
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*/
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(), 0x0);
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(),
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ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(),
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ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set dstg bits with data RAM */
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/* set rstg bits */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set dstg bits with byte enable (BE) RAM */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_dstg_ecc_address_r(),
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ltc_ltc0_lts0_dstg_ecc_address_info_ram_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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EXPECT_BUG(g->ops.ltc.intr.isr(g, 0));
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/* set tstg & rstg bits */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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EXPECT_BUG(g->ops.ltc.intr.isr(g, 0));
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/* set sec & ded error bits */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr_r(),
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ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() |
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ltc_ltcs_ltss_intr_ecc_ded_error_pending_f());
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/* set tstg bits */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* For branch coverage, set sec & ded error bits and make l2 flush succeed */
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save_func = g->ops.mm.cache.l2_flush;
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g->ops.mm.cache.l2_flush = mock_l2_flush;
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr_r(),
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ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() |
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ltc_ltcs_ltss_intr_ecc_ded_error_pending_f());
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/* set dstg bits */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(), 0);
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/* set sec error bits */
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save_func = g->ops.mm.cache.l2_flush;
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g->ops.mm.cache.l2_flush = mock_l2_flush;
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr_r(),
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ltc_ltcs_ltss_intr_ecc_sec_error_pending_f());
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g->ops.ltc.intr.isr(g, 0);
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g->ops.mm.cache.l2_flush = save_func;
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/* set ded error bits */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr_r(),
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ltc_ltcs_ltss_intr_ecc_ded_error_pending_f());
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g->ops.ltc.intr.isr(g, 0);
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/* For branch coverage, set sec error bits and make l2 flush fail */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr_r(),
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ltc_ltcs_ltss_intr_ecc_sec_error_pending_f());
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EXPECT_BUG(g->ops.ltc.intr.isr(g, 0));
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr_r(), 0);
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done:
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nvgpu_ltc_ecc_free(g);
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