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nvgpu: gk20a: MISRA Rule 21.2 header guard fixes

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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations caused by
include guards by renaming them to follow the convention,
'NVGPU_PARENT-DIR_HEADER_H'

JIRA NVGPU-1028

Change-Id: I478be317d067a75cdc8cb7fe9577a66d06318a11
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813068
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
smadhavan
2018-09-05 12:50:15 +05:30
committed by mobile promotions
parent 4451cf29d4
commit c4ac750e98
8 changed files with 26 additions and 26 deletions
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6
drivers/gpu/nvgpu/gk20a/ce2_gk20a.h
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@@ -23,8 +23,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __CE2_GK20A_H__
#define __CE2_GK20A_H__
#ifndef NVGPU_GK20A_CE2_GK20A_H
#define NVGPU_GK20A_CE2_GK20A_H
struct channel_gk20a;
struct tsg_gk20a;
@@ -153,4 +153,4 @@ int gk20a_ce_prepare_submit(u64 src_buf,
int request_operation,
u32 dma_copy_class);
#endif /*__CE2_GK20A_H__*/
#endif /*NVGPU_GK20A_CE2_GK20A_H*/

6
drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h
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@@ -24,8 +24,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _GK20A_CHANNEL_SYNC_H_
#define _GK20A_CHANNEL_SYNC_H_
#ifndef NVGPU_GK20A_CHANNEL_SYNC_GK20A_H
#define NVGPU_GK20A_CHANNEL_SYNC_GK20A_H
struct gk20a_channel_sync;
struct priv_cmd_entry;
@@ -109,4 +109,4 @@ struct gk20a_channel_sync *gk20a_channel_sync_create(struct channel_gk20a *c,
bool user_managed);
bool gk20a_channel_sync_needs_sync_framework(struct gk20a *g);
#endif
#endif /* NVGPU_GK20A_CHANNEL_SYNC_GK20A_H */

6
drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.h
View File

@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __FECS_TRACE_GK20A_H
#define __FECS_TRACE_GK20A_H
#ifndef NVGPU_GK20A_FECS_TRACE_GK20A_H
#define NVGPU_GK20A_FECS_TRACE_GK20A_H
struct gk20a;
struct channel_gk20a;
@@ -41,4 +41,4 @@ int gk20a_fecs_trace_disable(struct gk20a *g);
bool gk20a_fecs_trace_is_enabled(struct gk20a *g);
size_t gk20a_fecs_trace_buffer_size(struct gk20a *g);
#endif /* __FECS_TRACE_GK20A_H */
#endif /* NVGPU_GK20A_FECS_TRACE_GK20A_H */

6
drivers/gpu/nvgpu/gk20a/fence_gk20a.h
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@@ -23,8 +23,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _GK20A_FENCE_H_
#define _GK20A_FENCE_H_
#ifndef NVGPU_GK20A_FENCE_GK20A_H
#define NVGPU_GK20A_FENCE_GK20A_H
#include <nvgpu/types.h>
#include <nvgpu/kref.h>
@@ -97,4 +97,4 @@ bool gk20a_fence_is_expired(struct gk20a_fence *f);
bool gk20a_fence_is_valid(struct gk20a_fence *f);
int gk20a_fence_install_fd(struct gk20a_fence *f, int fd);
#endif
#endif /* NVGPU_GK20A_FENCE_GK20A_H */

6
drivers/gpu/nvgpu/gk20a/flcn_gk20a.h
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@@ -19,11 +19,11 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __FLCN_GK20A_H__
#define __FLCN_GK20A_H__
#ifndef NVGPU_GK20A_FLCN_GK20A_H
#define NVGPU_GK20A_FLCN_GK20A_H
void gk20a_falcon_ops(struct nvgpu_falcon *flcn);
int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn);
void gk20a_falcon_dump_stats(struct nvgpu_falcon *flcn);
#endif /* __FLCN_GK20A_H__ */
#endif /* NVGPU_GK20A_FLCN_GK20A_H */

8
drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h
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@@ -1,7 +1,7 @@
/*
* GK20A Graphics Context
*
* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -21,8 +21,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __GR_CTX_GK20A_H__
#define __GR_CTX_GK20A_H__
#ifndef NVGPU_GK20A_GR_CTX_GK20A_H
#define NVGPU_GK20A_GR_CTX_GK20A_H
#include <nvgpu/kmem.h>
@@ -203,4 +203,4 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr);
struct gpu_ops;
void gk20a_init_gr_ctx(struct gpu_ops *gops);
#endif /*__GR_CTX_GK20A_H__*/
#endif /*NVGPU_GK20A_GR_CTX_GK20A_H*/

8
drivers/gpu/nvgpu/gk20a/hal.h
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@@ -1,7 +1,7 @@
/*
* NVIDIA GPU Hardware Abstraction Layer functions definitions.
*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,11 +22,11 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __HAL_GPU__
#define __HAL_GPU__
#ifndef NVGPU_GK20A_HAL_H
#define NVGPU_GK20A_HAL_H
struct gk20a;
int gpu_init_hal(struct gk20a *g);
#endif /* __HAL_GPU__ */
#endif /* NVGPU_GK20A_HAL_H */

6
drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
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@@ -23,8 +23,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __PMU_GK20A_H__
#define __PMU_GK20A_H__
#ifndef NVGPU_GK20A_PMU_GK20A_H
#define NVGPU_GK20A_PMU_GK20A_H
#include <nvgpu/flcnif_cmn.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
@@ -75,4 +75,4 @@ void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
bool gk20a_pmu_is_engine_in_reset(struct gk20a *g);
int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset);
u32 gk20a_pmu_get_irqdest(struct gk20a *g);
#endif /*__PMU_GK20A_H__*/
#endif /*NVGPU_GK20A_PMU_GK20A_H*/