From c4dee40c494adb56624d5d28aee733f91e022ea3 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 8 Jun 2021 16:20:24 +0530 Subject: [PATCH] gpu: nvgpu: fix MISRA violations in common.gr 1. misra_c_2012_rule_8_6_violation: "gm20b_gr_init_fe_go_idle_timeout" is declared but never defined. Fix by adding config CONFIG_NVGPU_HAL_NON_FUSA for header declaration of "gm20b_gr_init_fe_go_idle_timeout" 2. misra_c_2012_rule_5_7_violation: Identifier "ops" is already used to represent a type. Fix by renaming local variable ops to nonstall_ops in gm20b_gr_intr_nonstall_isr() 3. missing_default: No default case found for the switch statement "switch (offset << 2)" Fix by adding break and default statements to switch case in gv11b_gr_intr_handle_sw_method() Jira NVGPU-6779 Change-Id: I8df097ec66479edcd2e81bf46bab5b5db52ac8c8 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2541246 (cherry picked from commit c4d9fe0449f8c6ee209051abfe58c6f3a745808d) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2543012 Reviewed-by: svcacv Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: svc_kernel_abi Reviewed-by: Alex Waterman Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h | 4 +- .../nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c | 6 +-- .../nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c | 50 +++++++++++++------ 3 files changed, 41 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h index a3d5c8b57..171cf7d32 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -53,7 +53,9 @@ int gm20b_gr_init_wait_idle(struct gk20a *g); int gm20b_gr_init_wait_fe_idle(struct gk20a *g); int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on); void gm20b_gr_init_override_context_reset(struct gk20a *g); +#ifdef CONFIG_NVGPU_HAL_NON_FUSA void gm20b_gr_init_fe_go_idle_timeout(struct gk20a *g, bool enable); +#endif void gm20b_gr_init_pipe_mode_override(struct gk20a *g, bool enable); void gm20b_gr_init_load_method_init(struct gk20a *g, struct netlist_av_list *sw_method_init); diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c index 301f9c2a7..1e38f0064 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c @@ -373,7 +373,7 @@ void gm20b_gr_intr_enable_interrupts(struct gk20a *g, bool enable) u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g) { - u32 ops = 0; + u32 nonstall_ops = 0; u32 gr_intr = nvgpu_readl(g, gr_intr_nonstall_r()); nvgpu_log(g, gpu_dbg_intr, "pgraph nonstall intr %08x", gr_intr); @@ -382,10 +382,10 @@ u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g) /* Clear the interrupt */ nvgpu_writel(g, gr_intr_nonstall_r(), gr_intr_nonstall_trap_pending_f()); - ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE | + nonstall_ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE | NVGPU_CIC_NONSTALL_OPS_POST_EVENTS); } - return ops; + return nonstall_ops; } #ifdef CONFIG_NVGPU_DEBUGGER diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c index 296f4efc7..b14e0f88b 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c @@ -179,6 +179,8 @@ void gv11b_gr_intr_set_shader_cut_collector(struct gk20a *g, u32 data) int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data) { + int err = -EFAULT; + nvgpu_log_fn(g, " "); if (class_num == VOLTA_COMPUTE_A) { @@ -186,56 +188,74 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, #ifdef CONFIG_NVGPU_HAL_NON_FUSA case NVC0C0_SET_SHADER_EXCEPTIONS: g->ops.gr.intr.set_shader_exceptions(g, data); - return 0; + err = 0; + break; #endif case NVC3C0_SET_SKEDCHECK: gv11b_gr_intr_set_skedcheck(g, data); - return 0; + err = 0; + break; case NVC3C0_SET_SHADER_CUT_COLLECTOR: gv11b_gr_intr_set_shader_cut_collector(g, data); - return 0; + err = 0; + break; + default: + err = -EINVAL; + break; } } - #if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS) if (class_num == VOLTA_A) { switch (offset << 2) { case NVC397_SET_SHADER_EXCEPTIONS: g->ops.gr.intr.set_shader_exceptions(g, data); - return 0; + err = 0; + break; case NVC397_SET_CIRCULAR_BUFFER_SIZE: g->ops.gr.set_circular_buffer_size(g, data); - return 0; + err = 0; + break; case NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE: g->ops.gr.set_alpha_circular_buffer_size(g, data); - return 0; + err = 0; + break; case NVC397_SET_GO_IDLE_TIMEOUT: gp10b_gr_intr_set_go_idle_timeout(g, data); - return 0; + err = 0; + break; case NVC097_SET_COALESCE_BUFFER_SIZE: gv11b_gr_intr_set_coalesce_buffer_size(g, data); - return 0; + err = 0; + break; case NVC397_SET_TEX_IN_DBG: gv11b_gr_intr_set_tex_in_dbg(g, data); - return 0; + err = 0; + break; case NVC397_SET_SKEDCHECK: gv11b_gr_intr_set_skedcheck(g, data); - return 0; + err = 0; + break; case NVC397_SET_BES_CROP_DEBUG3: g->ops.gr.set_bes_crop_debug3(g, data); - return 0; + err = 0; + break; case NVC397_SET_BES_CROP_DEBUG4: g->ops.gr.set_bes_crop_debug4(g, data); - return 0; + err = 0; + break; case NVC397_SET_SHADER_CUT_COLLECTOR: gv11b_gr_intr_set_shader_cut_collector(g, data); - return 0; + err = 0; + break; + default: + err = -EINVAL; + break; } } #endif - return -EINVAL; + return err; } void gv11b_gr_intr_handle_gcc_exception(struct gk20a *g, u32 gpc,