diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
index 7b98c80fb..0eaa23ab6 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
@@ -325,6 +325,26 @@ static int gk20a_tsg_event_id_ctrl(struct gk20a *g, struct tsg_gk20a *tsg,
 	return err;
 }
 
+static int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level)
+{
+	struct gk20a *g = tsg->g;
+	int ret;
+
+	switch (level) {
+	case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW:
+	case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
+	case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH:
+		ret = g->ops.fifo.set_runlist_interleave(g, tsg->tsgid,
+							true, 0, level);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret ? ret : g->ops.fifo.update_runlist(g, 0, ~0, true, true);
+}
+
 static void release_used_tsg(struct fifo_gk20a *f, struct tsg_gk20a *tsg)
 {
 	mutex_lock(&f->tsg_inuse_mutex);
@@ -520,6 +540,20 @@ long gk20a_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
 		break;
 		}
 
+	case NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE:
+		{
+		err = gk20a_busy(g->dev);
+		if (err) {
+			gk20a_err(dev_from_gk20a(g),
+			   "failed to host gk20a for ioctl cmd: 0x%x", cmd);
+			return err;
+		}
+		err = gk20a_tsg_set_runlist_interleave(tsg,
+			((struct nvgpu_runlist_interleave_args *)buf)->level);
+		gk20a_idle(g->dev);
+		break;
+		}
+
 	default:
 		gk20a_err(dev_from_gk20a(g),
 			   "unrecognized tsg gpu ioctl cmd: 0x%x",
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index cf89b9d8c..16d602617 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -465,11 +465,13 @@ struct nvgpu_gpu_get_gpu_time_args {
 	_IOW(NVGPU_TSG_IOCTL_MAGIC, 6, struct nvgpu_set_priority_args)
 #define NVGPU_IOCTL_TSG_EVENT_ID_CTRL \
 	_IOWR(NVGPU_TSG_IOCTL_MAGIC, 7, struct nvgpu_event_id_ctrl_args)
+#define NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE \
+	_IOW(NVGPU_TSG_IOCTL_MAGIC, 8, struct nvgpu_runlist_interleave_args)
 
 #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE	\
 	sizeof(struct nvgpu_event_id_ctrl_args)
 #define NVGPU_TSG_IOCTL_LAST		\
-	_IOC_NR(NVGPU_IOCTL_TSG_EVENT_ID_CTRL)
+	_IOC_NR(NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE)
 
 
 /*