From c50b39f5992ccc97cf9e29ca4a324bab0644c802 Mon Sep 17 00:00:00 2001
From: Debarshi Dutta <ddutta@nvidia.com>
Date: Mon, 5 Jul 2021 11:03:20 +0530
Subject: [PATCH] gpu: nvgpu: bvec for priv_ring

-Added BVEC coverage tests for priv_ring.
-Extended existing unit test to cover all possible equivalence classes
handling. All the classes are considered valid. Test is considered
passed as long as there are no BUGs.

Jira NVGPU-6405

Change-Id: Ia857e84c5e26856ee13d99d0c615db7f5a62e4a5
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2549223
(cherry picked from commit 1e6ffc1f3df6303c24b42534bd8b449b7b0e7677)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2556388
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
---
 userspace/units/priv_ring/nvgpu-priv_ring.c | 7 +++++++
 userspace/units/priv_ring/nvgpu-priv_ring.h | 8 ++++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/userspace/units/priv_ring/nvgpu-priv_ring.c b/userspace/units/priv_ring/nvgpu-priv_ring.c
index ef5bf2905..54607d9e5 100644
--- a/userspace/units/priv_ring/nvgpu-priv_ring.c
+++ b/userspace/units/priv_ring/nvgpu-priv_ring.c
@@ -21,6 +21,7 @@
  */
 
 #include <unit/unit.h>
+#include <unit/utils.h>
 #include <unit/io.h>
 #include <nvgpu/posix/io.h>
 #include <nvgpu/cic_mon.h>
@@ -377,6 +378,7 @@ int test_priv_ring_isr(struct unit_module *m, struct gk20a *g, void *args)
 }
 
 u32 error_codes[] = {
+	0U,
 	0xBADF1100U,
 	0xBADF1800U,
 	0xBADF1A00U,
@@ -389,6 +391,7 @@ u32 error_codes[] = {
 	0xBADF5100U,
 	0xBADF5500U,
 	0xBADF5600U,
+	U32_MAX,
 };
 
 int test_decode_error_code(struct unit_module *m, struct gk20a *g, void *args)
@@ -401,6 +404,10 @@ int test_decode_error_code(struct unit_module *m, struct gk20a *g, void *args)
 		g->ops.priv_ring.decode_error_code(g, error_codes[i]);
 	}
 
+	/* Call priv_ring ISR randomly on the full range */
+	u32 random_code = get_random_u32(1, U32_MAX - 1);
+	g->ops.priv_ring.decode_error_code(g, random_code);
+
 	return ret;
 }
 
diff --git a/userspace/units/priv_ring/nvgpu-priv_ring.h b/userspace/units/priv_ring/nvgpu-priv_ring.h
index 79a18b7a0..ff763f6f3 100644
--- a/userspace/units/priv_ring/nvgpu-priv_ring.h
+++ b/userspace/units/priv_ring/nvgpu-priv_ring.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -224,17 +224,21 @@ int test_priv_ring_isr(struct unit_module *m, struct gk20a *g, void *args);
  *
  * Description: Verify the priv_ring.decode_error_code HAL.
  *
- * Test Type: Feature, Error injection
+ * Test Type: Feature, Error injection, Boundary Value
  *
  * Targets: gops_priv_ring.decode_error_code, gp10b_decode_error_code
  *
  * Input: test_priv_ring_setup() has been executed.
+ * Equivalence classes:
+ * engine_id
+ * - Valid : {0 - U32_MAX}
  *
  * Steps:
  * - Call decode_error_code HAL with different error_codes covering all the
  *   branches (0xBADF1xxx, 0xBADF2xxx, 0xBADF3xxx, 0xBADF5xxx).
  * - Include error codes with reference the largest index for each of the error
  *   types.
+ * - Include boundary values and one random number in between the range [0 - U32_MAX]
  *
  * Output:
  * - UNIT_SUCCESS