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gpu: nvgpu: PMU & struct nvgpu_pmu clean up

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Some variables/defines of PMU are not used currenlty, so removed.
Moved some struct from pmu header file to respective unit.

removed pmu_fw.c file, which is not required anymore, missed removing
as part of fw unit task.

JIRA NVGPU-1972

Change-Id: I6334f7b2f47b1965780ddeaa41edac69972e6038
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094839
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-04-10 20:06:57 +05:30
committed by mobile promotions
parent 678cfdc608
commit c53c745b02
5 changed files with 6 additions and 1938 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/common/pmu/pmu.c
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@@ -384,7 +384,6 @@ static void nvgpu_remove_pmu_support(struct nvgpu_pmu *pmu)
nvgpu_mutex_destroy(&pmu->pmu_pg.elpg_mutex); nvgpu_mutex_destroy(&pmu->pmu_pg.elpg_mutex);
nvgpu_mutex_destroy(&pmu->pmu_pg.pg_mutex); nvgpu_mutex_destroy(&pmu->pmu_pg.pg_mutex);
nvgpu_mutex_destroy(&pmu->isr_mutex); nvgpu_mutex_destroy(&pmu->isr_mutex);
nvgpu_mutex_destroy(&pmu->pmu_copy_lock);
nvgpu_pmu_sequences_free(g, &pmu->sequences); nvgpu_pmu_sequences_free(g, &pmu->sequences);
nvgpu_pmu_mutexes_free(g, &pmu->mutexes); nvgpu_pmu_mutexes_free(g, &pmu->mutexes);
} }
@@ -427,11 +426,6 @@ int nvgpu_early_init_pmu_sw(struct gk20a *g, struct nvgpu_pmu *pmu)
goto init_failed; goto init_failed;
} }
err = nvgpu_mutex_init(&pmu->pmu_copy_lock);
if (err != 0) {
goto init_failed;
}
/* Allocate memory for pmu_perfmon */ /* Allocate memory for pmu_perfmon */
err = nvgpu_pmu_initialize_perfmon(g, pmu); err = nvgpu_pmu_initialize_perfmon(g, pmu);
if (err != 0) { if (err != 0) {

1885
drivers/gpu/nvgpu/common/pmu/pmu_fw.c
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File diff suppressed because it is too large Load Diff

7
drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h
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@@ -27,7 +27,6 @@ struct boardobjgrp;
struct gk20a; struct gk20a;
struct nvgpu_list_node; struct nvgpu_list_node;
/* ------------------------ Includes ----------------------------------------*/ /* ------------------------ Includes ----------------------------------------*/
#include <nvgpu/boardobj.h> #include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrpmask.h> #include <nvgpu/boardobjgrpmask.h>
@@ -102,6 +101,12 @@ int boardobjgrp_pmugetstatus_impl_v1(struct gk20a *g,
* Structure describing an PMU CMD for interacting with the representaition * Structure describing an PMU CMD for interacting with the representaition
* of this BOARDOBJGRP within the PMU. * of this BOARDOBJGRP within the PMU.
*/ */
struct pmu_surface {
struct nvgpu_mem vidmem_desc;
struct nvgpu_mem sysmem_desc;
struct flcn_mem_desc_v0 params;
};
struct boardobjgrp_pmu_cmd { struct boardobjgrp_pmu_cmd {
u8 id; u8 id;
u8 msgid; u8 msgid;

45
drivers/gpu/nvgpu/include/nvgpu/pmu.h
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@@ -52,41 +52,6 @@
#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6U #define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6U
#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEADU #define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEADU
/* Falcon Register index */
#define PMU_FALCON_REG_R0 (0U)
#define PMU_FALCON_REG_R1 (1U)
#define PMU_FALCON_REG_R2 (2U)
#define PMU_FALCON_REG_R3 (3U)
#define PMU_FALCON_REG_R4 (4U)
#define PMU_FALCON_REG_R5 (5U)
#define PMU_FALCON_REG_R6 (6U)
#define PMU_FALCON_REG_R7 (7U)
#define PMU_FALCON_REG_R8 (8U)
#define PMU_FALCON_REG_R9 (9U)
#define PMU_FALCON_REG_R10 (10U)
#define PMU_FALCON_REG_R11 (11U)
#define PMU_FALCON_REG_R12 (12U)
#define PMU_FALCON_REG_R13 (13U)
#define PMU_FALCON_REG_R14 (14U)
#define PMU_FALCON_REG_R15 (15U)
#define PMU_FALCON_REG_IV0 (16U)
#define PMU_FALCON_REG_IV1 (17U)
#define PMU_FALCON_REG_UNDEFINED (18U)
#define PMU_FALCON_REG_EV (19U)
#define PMU_FALCON_REG_SP (20U)
#define PMU_FALCON_REG_PC (21U)
#define PMU_FALCON_REG_IMB (22U)
#define PMU_FALCON_REG_DMB (23U)
#define PMU_FALCON_REG_CSW (24U)
#define PMU_FALCON_REG_CCR (25U)
#define PMU_FALCON_REG_SEC (26U)
#define PMU_FALCON_REG_CTX (27U)
#define PMU_FALCON_REG_EXCI (28U)
#define PMU_FALCON_REG_RSVD0 (29U)
#define PMU_FALCON_REG_RSVD1 (30U)
#define PMU_FALCON_REG_RSVD2 (31U)
#define PMU_FALCON_REG_SIZE (32U)
#define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32U #define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32U
#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64U #define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64U
@@ -211,8 +176,6 @@ struct nvgpu_pmu {
struct pmu_mutexes mutexes; struct pmu_mutexes mutexes;
struct nvgpu_mutex pmu_copy_lock;
struct nvgpu_allocator dmem; struct nvgpu_allocator dmem;
u32 mscg_stat; u32 mscg_stat;
@@ -230,14 +193,6 @@ struct nvgpu_pmu {
struct nvgpu_mutex isr_mutex; struct nvgpu_mutex isr_mutex;
bool isr_enabled; bool isr_enabled;
u32 override_done;
};
struct pmu_surface {
struct nvgpu_mem vidmem_desc;
struct nvgpu_mem sysmem_desc;
struct flcn_mem_desc_v0 params;
}; };
/*! /*!

1
drivers/gpu/nvgpu/include/nvgpu/pmu/fw.h
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@@ -30,7 +30,6 @@
struct nvgpu_pmu; struct nvgpu_pmu;
struct pmu_sequence; struct pmu_sequence;
struct pmu_super_surface; struct pmu_super_surface;
struct pmu_surface;
struct pmu_pg_cmd; struct pmu_pg_cmd;
struct boardobjgrp; struct boardobjgrp;
struct boardobjgrp_pmu_cmd; struct boardobjgrp_pmu_cmd;