From c57cf00aa04ae2fdb5a627a7a833cfc1d8017ba9 Mon Sep 17 00:00:00 2001 From: Abdul Salam Date: Thu, 17 Jan 2019 16:24:56 +0530 Subject: [PATCH] gpu: nvgpu: Add quantization to slave VF Points All slave clock should be quantized as per step size. TU104 has 15Mhz as step size. Enable clk_arb without enabling clk_freq_controller. clk_freq_controller is not needed for Auto use case. Increase the maxclk only when master is less that slave clock. This is needed when gpcclk is less than slave P0 min. Use get_status to get Vim and use it for change sequencer. Add support for Device Events Bug 200454682 Bug 2481917 Change-Id: Ie0c404f4b77e41f6a1719b52d6e29a5ac757b41b Signed-off-by: Abdul Salam Reviewed-on: https://git-master.nvidia.com/r/1994831 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Vaikundanathan S Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/init/nvgpu_init.c | 2 +- drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c | 4 +- .../gpu/nvgpu/common/pmu/clk/clk_vf_point.c | 48 +++++++++++++------ .../gpu/nvgpu/common/pmu/clk/clk_vf_point.h | 3 +- drivers/gpu/nvgpu/tu104/hal_tu104.c | 1 + 5 files changed, 41 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 4d8624f0e..5532148f9 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -534,7 +534,7 @@ int gk20a_init_gpu_characteristics(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG, true); - if (g->ops.clk_arb.get_arbiter_clk_domains != NULL && + if (g->ops.clk_arb.get_arbiter_clk_domains != NULL || g->ops.clk.support_clk_freq_controller) { nvgpu_set_enabled(g, NVGPU_SUPPORT_CLOCK_CONTROLS, true); } diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c index f0dc32133..72689969c 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1764,6 +1764,8 @@ static int getslaveclk_prog_1x_master(struct gk20a *g, return -EINVAL; } *pclkmhz = (masterclkmhz * pslaveents->ratio)/100U; + /* Floor/Quantize all the slave clocks to the multiple of step size*/ + *pclkmhz = (*pclkmhz / FREQ_STEP_SIZE_MHZ) * FREQ_STEP_SIZE_MHZ; } else { /* only support ratio for now */ return -EINVAL; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c index 72c976ea4..9a8f81dba 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,6 +28,7 @@ #include #include #include +#include #include "clk.h" #include "clk_vf_point.h" @@ -498,6 +499,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq u32 max_clkmhz; u16 max_ratio; struct clk_set_info *p0_info; + u32 vmin_uv = 0; (void) memset(&change_input, 0, sizeof(struct ctrl_perf_change_seq_change_input)); @@ -540,9 +542,11 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq } change_input.clk[i].clk_freq_khz = (u32)vf_point->xbar_mhz * 1000U; change_input.clk_domains_mask.super.data[0] |= (u32) BIT(i); - max_clkmhz = (((u32)vf_point->xbar_mhz * 100U)/ (u32)max_ratio); - if (gpcclk_clkmhz < max_clkmhz) { - gpcclk_clkmhz = max_clkmhz; + if (vf_point->gpc_mhz < vf_point->xbar_mhz) { + max_clkmhz = (((u32)vf_point->xbar_mhz * 100U) / (u32)max_ratio); + if (gpcclk_clkmhz < max_clkmhz) { + gpcclk_clkmhz = max_clkmhz; + } } break; case CTRL_CLK_DOMAIN_SYSCLK: @@ -561,9 +565,11 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq } change_input.clk[i].clk_freq_khz = (u32)vf_point->sys_mhz * 1000U; change_input.clk_domains_mask.super.data[0] |= (u32) BIT(i); - max_clkmhz = (((u32)vf_point->sys_mhz * 100U)/ (u32)max_ratio); - if (gpcclk_clkmhz < max_clkmhz) { - gpcclk_clkmhz = max_clkmhz; + if (vf_point->gpc_mhz < vf_point->sys_mhz) { + max_clkmhz = (((u32)vf_point->sys_mhz * 100U) / (u32)max_ratio); + if (gpcclk_clkmhz < max_clkmhz) { + gpcclk_clkmhz = max_clkmhz; + } } break; case CTRL_CLK_DOMAIN_NVDCLK: @@ -582,9 +588,11 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq } change_input.clk[i].clk_freq_khz = (u32)vf_point->nvd_mhz * 1000U; change_input.clk_domains_mask.super.data[0] |= (u32) BIT(i); - max_clkmhz = (((u32)vf_point->nvd_mhz * 100U)/ (u32)max_ratio); - if (gpcclk_clkmhz < max_clkmhz) { - gpcclk_clkmhz = max_clkmhz; + if (vf_point->gpc_mhz < vf_point->nvd_mhz) { + max_clkmhz = (((u32)vf_point->nvd_mhz * 100U) / (u32)max_ratio); + if (gpcclk_clkmhz < max_clkmhz) { + gpcclk_clkmhz = max_clkmhz; + } } break; case CTRL_CLK_DOMAIN_HOSTCLK: @@ -603,9 +611,11 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq } change_input.clk[i].clk_freq_khz = (u32)vf_point->host_mhz * 1000U; change_input.clk_domains_mask.super.data[0] |= (u32) BIT(i); - max_clkmhz = (((u32)vf_point->host_mhz * 100U)/ (u32)max_ratio); - if (gpcclk_clkmhz < max_clkmhz) { - gpcclk_clkmhz = max_clkmhz; + if (vf_point->gpc_mhz < vf_point->host_mhz) { + max_clkmhz = (((u32)vf_point->host_mhz * 100U) / (u32)max_ratio); + if (gpcclk_clkmhz < max_clkmhz) { + gpcclk_clkmhz = max_clkmhz; + } } break; default: @@ -620,7 +630,17 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq status = clk_domain_freq_to_volt(g, gpcclk_domain, &gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC); - gpcclk_voltuv += VMIN_PAD_UV; + + status = g->ops.pmu_ver.volt.volt_get_vmin(g, &vmin_uv); + if (status != 0) { + nvgpu_err(g, "Failed to execute Vmin get_status status=0x%x", + status); + } + if ((status == 0) && (vmin_uv > gpcclk_voltuv)) { + gpcclk_voltuv = vmin_uv; + nvgpu_log_fn(g, "Vmin is higher than evaluated Volt"); + } + change_input.volt[0].voltage_uv = gpcclk_voltuv; change_input.volt[0].voltage_min_noise_unaware_uv = gpcclk_voltuv; change_input.volt_rails_mask.super.data[0] = 1U; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h index 1ba9637fb..3e36f8b1a 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -30,6 +30,7 @@ #include #define VMIN_PAD_UV 50000U +#define FREQ_STEP_SIZE_MHZ 15U int clk_vf_point_cache(struct gk20a *g); struct nvgpu_clk_arb; diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index ebd5b717b..94ca19ca9 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -312,6 +312,7 @@ static int tu104_init_gpu_characteristics(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true); } nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true); + nvgpu_set_enabled(g, NVGPU_SUPPORT_DEVICE_EVENTS, true); return 0; }