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gpu: nvgpu: move gr config structs to priv header

Browse Source 
Move sm_info and nvgpu_gr_config struts to a private
header and add APIs to access member fields.

JIRA NVGPU-3060

Change-Id: I90f44333f19cb8cb939c0a0f90d9a03f6c036080
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2091563
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Nitin Kumbhar
2019-04-07 12:50:43 +05:30
committed by mobile promotions
parent 364c780469
commit c649ca9fd6
21 changed files with 292 additions and 144 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/common/gr/fs_state.c
View File

@@ -96,7 +96,7 @@ int nvgpu_gr_fs_state_init(struct gk20a *g)
}
if (g->ops.gr.config.init_sm_id_table != NULL) {
err = g->ops.gr.config.init_sm_id_table(gr_config);
err = g->ops.gr.config.init_sm_id_table(g, gr_config);
if (err != 0) {
return err;
}
@@ -111,8 +111,8 @@ int nvgpu_gr_fs_state_init(struct gk20a *g)
sm_id++) {
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(gr_config, sm_id);
tpc_index = sm_info->tpc_index;
gpc_index = sm_info->gpc_index;
tpc_index = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
gpc_index = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
g->ops.gr.init.sm_id_numbering(g, gpc_index, tpc_index, sm_id);
}

76
drivers/gpu/nvgpu/common/gr/gr_config.c
View File

@@ -24,6 +24,8 @@
#include <nvgpu/io.h>
#include <nvgpu/gr/config.h>
#include "common/gr/gr_config_priv.h"
struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g)
{
struct nvgpu_gr_config *config;
@@ -261,6 +263,11 @@ u32 nvgpu_gr_config_get_map_tile_count(struct nvgpu_gr_config *config, u32 index
return config->map_tiles[index];
}
u8 *nvgpu_gr_config_get_map_tiles(struct nvgpu_gr_config *config)
{
return config->map_tiles;
}
u32 nvgpu_gr_config_get_map_row_offset(struct nvgpu_gr_config *config)
{
return config->map_row_offset;
@@ -531,6 +538,11 @@ u32 nvgpu_gr_config_get_gpc_ppc_count(struct nvgpu_gr_config *config,
return config->gpc_ppc_count[gpc_index];
}
u32 *nvgpu_gr_config_get_gpc_tpc_count_base(struct nvgpu_gr_config *config)
{
return config->gpc_tpc_count;
}
u32 nvgpu_gr_config_get_gpc_tpc_count(struct nvgpu_gr_config *config,
u32 gpc_index)
{
@@ -552,12 +564,23 @@ u32 nvgpu_gr_config_get_pes_tpc_count(struct nvgpu_gr_config *config,
return config->pes_tpc_count[pes_index][gpc_index];
}
u32 *nvgpu_gr_config_get_gpc_tpc_mask_base(struct nvgpu_gr_config *config)
{
return config->gpc_tpc_mask;
}
u32 nvgpu_gr_config_get_gpc_tpc_mask(struct nvgpu_gr_config *config,
u32 gpc_index)
{
return config->gpc_tpc_mask[gpc_index];
}
void nvgpu_gr_config_set_gpc_tpc_mask(struct nvgpu_gr_config *config,
u32 gpc_index, u32 val)
{
config->gpc_tpc_mask[gpc_index] = val;
}
u32 nvgpu_gr_config_get_gpc_skip_mask(struct nvgpu_gr_config *config,
u32 gpc_index)
{
@@ -580,8 +603,57 @@ u32 nvgpu_gr_config_get_no_of_sm(struct nvgpu_gr_config *config)
return config->no_of_sm;
}
struct sm_info *
nvgpu_gr_config_get_sm_info(struct nvgpu_gr_config *config, u32 sm_id)
void nvgpu_gr_config_set_no_of_sm(struct nvgpu_gr_config *config, u32 no_of_sm)
{
config->no_of_sm = no_of_sm;
}
struct sm_info *nvgpu_gr_config_get_sm_info(struct nvgpu_gr_config *config,
u32 sm_id)
{
return &config->sm_to_cluster[sm_id];
}
u32 nvgpu_gr_config_get_sm_info_gpc_index(struct sm_info *sm_info)
{
return sm_info->gpc_index;
}
void nvgpu_gr_config_set_sm_info_gpc_index(struct sm_info *sm_info,
u32 gpc_index)
{
sm_info->gpc_index = gpc_index;
}
u32 nvgpu_gr_config_get_sm_info_tpc_index(struct sm_info *sm_info)
{
return sm_info->tpc_index;
}
void nvgpu_gr_config_set_sm_info_tpc_index(struct sm_info *sm_info,
u32 tpc_index)
{
sm_info->tpc_index = tpc_index;
}
u32 nvgpu_gr_config_get_sm_info_global_tpc_index(struct sm_info *sm_info)
{
return sm_info->global_tpc_index;
}
void nvgpu_gr_config_set_sm_info_global_tpc_index(struct sm_info *sm_info,
u32 global_tpc_index)
{
sm_info->global_tpc_index = global_tpc_index;
}
u32 nvgpu_gr_config_get_sm_info_sm_index(struct sm_info *sm_info)
{
return sm_info->sm_index;
}
void nvgpu_gr_config_set_sm_info_sm_index(struct sm_info *sm_info,
u32 sm_index)
{
sm_info->sm_index = sm_index;
}

73
drivers/gpu/nvgpu/common/gr/gr_config_priv.h Normal file
View File

@@ -0,0 +1,73 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_GR_CONFIG_PRIV_H
#define NVGPU_GR_CONFIG_PRIV_H
#include <nvgpu/types.h>
#define GK20A_GR_MAX_PES_PER_GPC 3U
struct gk20a;
struct sm_info {
u32 gpc_index;
u32 tpc_index;
u32 sm_index;
u32 global_tpc_index;
};
struct nvgpu_gr_config {
struct gk20a *g;
u32 max_gpc_count;
u32 max_tpc_per_gpc_count;
u32 max_zcull_per_gpc_count;
u32 max_tpc_count;
u32 gpc_count;
u32 tpc_count;
u32 ppc_count;
u32 zcb_count;
u32 pe_count_per_gpc;
u32 sm_count_per_tpc;
u32 *gpc_ppc_count;
u32 *gpc_tpc_count;
u32 *gpc_zcb_count;
u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC];
u32 gpc_mask;
u32 *gpc_tpc_mask;
u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_skip_mask;
u8 *map_tiles;
u32 map_tile_count;
u32 map_row_offset;
u32 no_of_sm;
struct sm_info *sm_to_cluster;
};
#endif /* NVGPU_GR_CONFIG_PRIV_H */

2
drivers/gpu/nvgpu/common/gr/zcull.c
View File

@@ -91,7 +91,7 @@ int nvgpu_gr_zcull_init_hw(struct gk20a *g,
u32 map_tile_count;
int ret = 0;
if (gr_config->map_tiles == NULL) {
if (nvgpu_gr_config_get_map_tiles(gr_config) == NULL) {
return -1;
}

11
drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c
View File

@@ -52,6 +52,7 @@
#include "common/vgpu/perf/cyclestats_snapshot_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
#include "common/gr/gr_config_priv.h"
#include "common/gr/zcull_priv.h"
#include "common/gr/zbc_priv.h"
@@ -1111,12 +1112,12 @@ void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
nvgpu_mutex_release(&g->dbg_sessions_lock);
}
int vgpu_gr_init_sm_id_table(struct nvgpu_gr_config *gr_config)
int vgpu_gr_init_sm_id_table(struct gk20a *g, struct nvgpu_gr_config *gr_config)
{
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_vsms_mapping_params *p = &msg.params.vsms_mapping;
struct tegra_vgpu_vsms_mapping_entry *entry;
struct vgpu_priv_data *priv = vgpu_get_priv_data(gr_config->g);
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
struct sm_info *sm_info;
int err;
size_t oob_size;
@@ -1125,11 +1126,11 @@ int vgpu_gr_init_sm_id_table(struct nvgpu_gr_config *gr_config)
u32 max_sm;
msg.cmd = TEGRA_VGPU_CMD_GET_VSMS_MAPPING;
msg.handle = vgpu_get_handle(gr_config->g);
msg.handle = vgpu_get_handle(g);
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err ? err : msg.ret;
if (err) {
nvgpu_err(gr_config->g,
nvgpu_err(g,
"get vsms mapping failed err %d", err);
return err;
}
@@ -1171,7 +1172,7 @@ int vgpu_gr_init_fs_state(struct gk20a *g)
return -EINVAL;
}
return g->ops.gr.config.init_sm_id_table(g->gr.config);
return g->ops.gr.config.init_sm_id_table(g, g->gr.config);
}
int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable)

3
drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h
View File

@@ -77,7 +77,8 @@ int vgpu_gr_suspend_contexts(struct gk20a *g,
int vgpu_gr_resume_contexts(struct gk20a *g,
struct dbg_session_gk20a *dbg_s,
int *ctx_resident_ch_fd);
int vgpu_gr_init_sm_id_table(struct nvgpu_gr_config *gr_config);
int vgpu_gr_init_sm_id_table(struct gk20a *g,
struct nvgpu_gr_config *gr_config);
int vgpu_gr_init_fs_state(struct gk20a *g);
int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable);
void vgpu_gr_init_cyclestats(struct gk20a *g);

16
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -2798,8 +2798,8 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
continue;
}
sm_info = nvgpu_gr_config_get_sm_info(g->gr.config, sm_id);
gpc = sm_info->gpc_index;
tpc = sm_info->tpc_index;
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
tpc_offset = tpc_in_gpc_stride * tpc;
gpc_offset = gpc_stride * gpc;
@@ -2996,9 +2996,9 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state)
for (sm_id = 0; sm_id < no_of_sm; sm_id++) {
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(g->gr.config, sm_id);
gpc = sm_info->gpc_index;
tpc = sm_info->tpc_index;
sm = sm_info->sm_index;
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
sm = nvgpu_gr_config_get_sm_info_sm_index(sm_info);
err = g->ops.gr.lock_down_sm(g, gpc, tpc, sm,
global_mask, false);
@@ -3075,8 +3075,10 @@ u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g)
for (sm_id = 0; sm_id < no_of_sm; sm_id++) {
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(g->gr.config, sm_id);
tpc_offset = tpc_in_gpc_stride * sm_info->tpc_index;
gpc_offset = gpc_stride * sm_info->gpc_index;
tpc_offset = tpc_in_gpc_stride *
nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
gpc_offset = gpc_stride *
nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
offset = tpc_offset + gpc_offset;
regval = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_en_r() +

12
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -441,8 +441,8 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n",
gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r()));
if ((gr->config->gpc_tpc_count != NULL) &&
(gr->config->gpc_tpc_count[0] == 2U)) {
if ((nvgpu_gr_config_get_gpc_tpc_count_base(gr->config) != NULL) &&
(nvgpu_gr_config_get_gpc_tpc_count(gr->config, 0) == 2U)) {
gk20a_debug_output(o,
"NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n",
gk20a_readl(g,
@@ -609,8 +609,8 @@ void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
for (sm_id = 0; sm_id < no_of_sm; sm_id++) {
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(gr->config, sm_id);
gpc = sm_info->gpc_index;
tpc = sm_info->tpc_index;
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
tpc_offset = tpc_in_gpc_stride * tpc;
gpc_offset = gpc_stride * gpc;
@@ -753,8 +753,8 @@ int gm20b_gr_clear_sm_error_state(struct gk20a *g,
if (gk20a_is_channel_ctx_resident(ch)) {
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(g->gr.config, sm_id);
gpc = sm_info->gpc_index;
tpc = sm_info->tpc_index;
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;

4
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -563,8 +563,8 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n",
gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r()));
if ((gr->config->gpc_tpc_count != NULL) &&
(gr->config->gpc_tpc_count[0] == 2U)) {
if ((nvgpu_gr_config_get_gpc_tpc_count_base(gr->config) != NULL) &&
(nvgpu_gr_config_get_gpc_tpc_count(gr->config, 0) == 2U)) {
gk20a_debug_output(o,
"NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n",
gk20a_readl(g,

30
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1146,8 +1146,8 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n",
gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r()));
if ((gr->config->gpc_tpc_count != NULL) &&
(gr->config->gpc_tpc_count[0] == 2U)) {
if ((nvgpu_gr_config_get_gpc_tpc_count_base(gr->config) != NULL) &&
(nvgpu_gr_config_get_gpc_tpc_count(gr->config, 0) == 2U)) {
gk20a_debug_output(o,
"NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n",
gk20a_readl(g,
@@ -1779,9 +1779,9 @@ void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
for (sm_id = 0; sm_id < no_of_sm; sm_id++) {
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(gr->config, sm_id);
gpc = sm_info->gpc_index;
tpc = sm_info->tpc_index;
sm = sm_info->sm_index;
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
sm = nvgpu_gr_config_get_sm_info_sm_index(sm_info);
offset = nvgpu_gr_gpc_offset(g, gpc) +
nvgpu_gr_tpc_offset(g, tpc) +
@@ -1858,15 +1858,15 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
}
sm_info = nvgpu_gr_config_get_sm_info(g->gr.config, sm_id);
gpc = sm_info->gpc_index;
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
if (g->ops.gr.get_nonpes_aware_tpc != NULL) {
tpc = g->ops.gr.get_nonpes_aware_tpc(g,
sm_info->gpc_index,
sm_info->tpc_index);
nvgpu_gr_config_get_sm_info_gpc_index(sm_info),
nvgpu_gr_config_get_sm_info_tpc_index(sm_info));
} else {
tpc = sm_info->tpc_index;
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
}
sm = sm_info->sm_index;
sm = nvgpu_gr_config_get_sm_info_sm_index(sm_info);
reg_offset = nvgpu_gr_gpc_offset(g, gpc) +
nvgpu_gr_tpc_offset(g, tpc) +
@@ -3295,15 +3295,15 @@ int gv11b_gr_clear_sm_error_state(struct gk20a *g,
if (gk20a_is_channel_ctx_resident(ch)) {
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(g->gr.config, sm_id);
gpc = sm_info->gpc_index;
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
if (g->ops.gr.get_nonpes_aware_tpc != NULL) {
tpc = g->ops.gr.get_nonpes_aware_tpc(g,
sm_info->gpc_index,
sm_info->tpc_index);
nvgpu_gr_config_get_sm_info_gpc_index(sm_info),
nvgpu_gr_config_get_sm_info_tpc_index(sm_info));
} else {
tpc = sm_info->tpc_index;
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
}
sm = sm_info->sm_index;
sm = nvgpu_gr_config_get_sm_info_sm_index(sm_info);
offset = nvgpu_gr_gpc_offset(g, gpc) +
nvgpu_gr_tpc_offset(g, tpc) +

19
drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.c
View File

@@ -28,7 +28,8 @@
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
int gm20b_gr_config_init_sm_id_table(struct nvgpu_gr_config *gr_config)
int gm20b_gr_config_init_sm_id_table(struct gk20a *g,
struct nvgpu_gr_config *gr_config)
{
u32 gpc, tpc;
u32 sm_id = 0;
@@ -41,15 +42,15 @@ int gm20b_gr_config_init_sm_id_table(struct nvgpu_gr_config *gr_config)
if (tpc < nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc)) {
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(gr_config, sm_id);
sm_info->tpc_index = tpc;
sm_info->gpc_index = gpc;
sm_info->sm_index = 0;
sm_info->global_tpc_index = sm_id;
nvgpu_gr_config_set_sm_info_tpc_index(sm_info, tpc);
nvgpu_gr_config_set_sm_info_gpc_index(sm_info, gpc);
nvgpu_gr_config_set_sm_info_sm_index(sm_info, 0);
nvgpu_gr_config_set_sm_info_global_tpc_index(sm_info, sm_id);
sm_id++;
}
}
}
gr_config->no_of_sm = sm_id;
nvgpu_gr_config_set_no_of_sm(gr_config, sm_id);
return 0;
}
@@ -61,7 +62,8 @@ u32 gm20b_gr_config_get_gpc_tpc_mask(struct gk20a *g,
/* Toggle the bits of NV_FUSE_STATUS_OPT_TPC_GPC */
val = g->ops.fuse.fuse_status_opt_tpc_gpc(g, gpc_index);
return (~val) & (BIT32(config->max_tpc_per_gpc_count) - 1U);
return (~val) &
(BIT32(nvgpu_gr_config_get_max_tpc_per_gpc_count(config)) - 1U);
}
u32 gm20b_gr_config_get_tpc_count_in_gpc(struct gk20a *g,
@@ -117,5 +119,6 @@ u32 gm20b_gr_config_get_gpc_mask(struct gk20a *g,
*/
val = g->ops.fuse.fuse_status_opt_gpc(g);
return (~val) & (BIT32(config->max_gpc_count) - 1U);
return (~val) &
(BIT32(nvgpu_gr_config_get_max_gpc_count(config)) - 1U);
}

3
drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h
View File

@@ -28,7 +28,8 @@
struct gk20a;
struct nvgpu_gr_config;
int gm20b_gr_config_init_sm_id_table(struct nvgpu_gr_config *gr_config);
int gm20b_gr_config_init_sm_id_table(struct gk20a *g,
struct nvgpu_gr_config *gr_config);
u32 gm20b_gr_config_get_gpc_tpc_mask(struct gk20a *g,
struct nvgpu_gr_config *config, u32 gpc_index);
u32 gm20b_gr_config_get_tpc_count_in_gpc(struct gk20a *g,

58
drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c
View File

@@ -30,7 +30,8 @@
* Estimate performance if the given logical TPC in the given logical GPC were
* removed.
*/
static int gr_gv100_scg_estimate_perf(struct nvgpu_gr_config *gr_config,
static int gr_gv100_scg_estimate_perf(struct gk20a *g,
struct nvgpu_gr_config *gr_config,
unsigned long *gpc_tpc_mask,
u32 disable_gpc_id, u32 disable_tpc_id,
int *perf)
@@ -57,8 +58,8 @@ static int gr_gv100_scg_estimate_perf(struct nvgpu_gr_config *gr_config,
bool is_tpc_removed_pes = false;
u32 max_tpc_gpc = 0U;
u32 num_tpc_mask;
u32 *num_tpc_gpc = nvgpu_kzalloc(gr_config->g, sizeof(u32) *
nvgpu_get_litter_value(gr_config->g, GPU_LIT_NUM_GPCS));
u32 *num_tpc_gpc = nvgpu_kzalloc(g, sizeof(u32) *
nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS));
if (num_tpc_gpc == NULL) {
return -ENOMEM;
@@ -171,11 +172,12 @@ static int gr_gv100_scg_estimate_perf(struct nvgpu_gr_config *gr_config,
(world_scale * scg_world_perf) +
(tpc_scale * tpc_balance);
free_resources:
nvgpu_kfree(gr_config->g, num_tpc_gpc);
nvgpu_kfree(g, num_tpc_gpc);
return err;
}
int gv100_gr_config_init_sm_id_table(struct nvgpu_gr_config *gr_config)
int gv100_gr_config_init_sm_id_table(struct gk20a *g,
struct nvgpu_gr_config *gr_config)
{
unsigned long tpc;
u32 gpc, sm, pes, gtpc;
@@ -191,20 +193,20 @@ int gv100_gr_config_init_sm_id_table(struct nvgpu_gr_config *gr_config)
return -ENOMEM;
}
gpc_table = nvgpu_kzalloc(gr_config->g,
gpc_table = nvgpu_kzalloc(g,
nvgpu_gr_config_get_tpc_count(gr_config) *
sizeof(u32));
tpc_table = nvgpu_kzalloc(gr_config->g,
tpc_table = nvgpu_kzalloc(g,
nvgpu_gr_config_get_tpc_count(gr_config) *
sizeof(u32));
gpc_tpc_mask = nvgpu_kzalloc(gr_config->g,
gpc_tpc_mask = nvgpu_kzalloc(g,
sizeof(unsigned long) *
nvgpu_get_litter_value(gr_config->g, GPU_LIT_NUM_GPCS));
nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS));
if ((gpc_table == NULL) ||
(tpc_table == NULL) ||
(gpc_tpc_mask == NULL)) {
nvgpu_err(gr_config->g, "Error allocating memory for sm tables");
nvgpu_err(g, "Error allocating memory for sm tables");
err = -ENOMEM;
goto exit_build_table;
}
@@ -224,11 +226,11 @@ int gv100_gr_config_init_sm_id_table(struct nvgpu_gr_config *gr_config)
for_each_set_bit(tpc, &gpc_tpc_mask[gpc],
nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc)) {
perf = -1;
err = gr_gv100_scg_estimate_perf(gr_config,
err = gr_gv100_scg_estimate_perf(g, gr_config,
gpc_tpc_mask, gpc, tpc, &perf);
if (err != 0) {
nvgpu_err(gr_config->g,
nvgpu_err(g,
"Error while estimating perf");
goto exit_build_table;
}
@@ -248,27 +250,29 @@ int gv100_gr_config_init_sm_id_table(struct nvgpu_gr_config *gr_config)
u32 index = sm_id + sm;
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(gr_config, index);
sm_info->gpc_index = gpc_table[tpc];
sm_info->tpc_index = tpc_table[tpc];
sm_info->sm_index = sm;
sm_info->global_tpc_index = tpc;
nvgpu_gr_config_set_sm_info_gpc_index(sm_info,
gpc_table[tpc]);
nvgpu_gr_config_set_sm_info_tpc_index(sm_info,
tpc_table[tpc]);
nvgpu_gr_config_set_sm_info_sm_index(sm_info, sm);
nvgpu_gr_config_set_sm_info_global_tpc_index(sm_info, tpc);
nvgpu_log_info(gr_config->g,
nvgpu_log_info(g,
"gpc : %d tpc %d sm_index %d global_index: %d",
sm_info->gpc_index,
sm_info->tpc_index,
sm_info->sm_index,
sm_info->global_tpc_index);
nvgpu_gr_config_get_sm_info_gpc_index(sm_info),
nvgpu_gr_config_get_sm_info_tpc_index(sm_info),
nvgpu_gr_config_get_sm_info_sm_index(sm_info),
nvgpu_gr_config_get_sm_info_global_tpc_index(sm_info));
}
}
gr_config->no_of_sm = num_sm;
nvgpu_log_info(gr_config->g, " total number of sm = %d",
gr_config->no_of_sm);
nvgpu_gr_config_set_no_of_sm(gr_config, num_sm);
nvgpu_log_info(g, " total number of sm = %d", num_sm);
exit_build_table:
nvgpu_kfree(gr_config->g, gpc_table);
nvgpu_kfree(gr_config->g, tpc_table);
nvgpu_kfree(gr_config->g, gpc_tpc_mask);
nvgpu_kfree(g, gpc_table);
nvgpu_kfree(g, tpc_table);
nvgpu_kfree(g, gpc_tpc_mask);
return err;
}

3
drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.h
View File

@@ -28,6 +28,7 @@
struct gk20a;
struct nvgpu_gr_config;
int gv100_gr_config_init_sm_id_table(struct nvgpu_gr_config *gr_config);
int gv100_gr_config_init_sm_id_table(struct gk20a *g,
struct nvgpu_gr_config *gr_config);
#endif /* NVGPU_GR_CONFIG_GV100_H */

8
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
View File

@@ -238,8 +238,10 @@ int gm20b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
}
sm_info =
nvgpu_gr_config_get_sm_info(gr_config, sm_id);
gpc_index = sm_info->gpc_index;
tpc_index = sm_info->tpc_index;
gpc_index =
nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc_index =
nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
bits = gr_cwd_gpc_tpc_id_gpc0_f(gpc_index) |
gr_cwd_gpc_tpc_id_tpc0_f(tpc_index);
@@ -272,7 +274,7 @@ int gm20b_gr_init_rop_mapping(struct gk20a *g,
u32 map0, map1, map2, map3, map4, map5;
u32 tpc_cnt;
if (gr_config->map_tiles == NULL) {
if (nvgpu_gr_config_get_map_tiles(gr_config) == NULL) {
return -1;
}

6
drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
View File

@@ -109,8 +109,10 @@ int gp10b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
}
sm_info =
nvgpu_gr_config_get_sm_info(gr_config, sm_id);
gpc_index = sm_info->gpc_index;
tpc_index = sm_info->tpc_index;
gpc_index =
nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc_index =
nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
bits = gr_cwd_gpc_tpc_id_gpc0_f(gpc_index) |
gr_cwd_gpc_tpc_id_tpc0_f(tpc_index);

11
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c
View File

@@ -466,7 +466,8 @@ void gv11b_gr_init_sm_id_numbering(struct gk20a *g,
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(g->gr.config, smid);
global_tpc_index = sm_info->global_tpc_index;
global_tpc_index =
nvgpu_gr_config_get_sm_info_global_tpc_index(sm_info);
tpc = g->ops.gr.get_nonpes_aware_tpc(g, gpc, tpc);
tpc_offset = tpc_in_gpc_stride * tpc;
@@ -509,8 +510,10 @@ int gv11b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
}
sm_info =
nvgpu_gr_config_get_sm_info(gr_config, sm_id);
gpc_index = sm_info->gpc_index;
tpc_index = sm_info->tpc_index;
gpc_index =
nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc_index =
nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
bits = gr_cwd_gpc_tpc_id_gpc0_f(gpc_index) |
gr_cwd_gpc_tpc_id_tpc0_f(tpc_index);
@@ -547,7 +550,7 @@ int gv11b_gr_init_rop_mapping(struct gk20a *g,
nvgpu_log_fn(g, " ");
if (gr_config->map_tiles == NULL) {
if (nvgpu_gr_config_get_map_tiles(gr_config) == NULL) {
return -1;
}

3
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -533,7 +533,8 @@ struct gpu_ops {
struct nvgpu_gr_config *config, u32 gpc_index,
u32 pes_index);
u32 (*get_pd_dist_skip_table_size)(void);
int (*init_sm_id_table)(struct nvgpu_gr_config *gr_config);
int (*init_sm_id_table)(struct gk20a *g,
struct nvgpu_gr_config *gr_config);
} config;
struct {

67
drivers/gpu/nvgpu/include/nvgpu/gr/config.h
View File

@@ -25,50 +25,9 @@
#include <nvgpu/types.h>
#define GK20A_GR_MAX_PES_PER_GPC 3U
struct gk20a;
struct sm_info {
u32 gpc_index;
u32 tpc_index;
u32 sm_index;
u32 global_tpc_index;
};
struct nvgpu_gr_config {
struct gk20a *g;
u32 max_gpc_count;
u32 max_tpc_per_gpc_count;
u32 max_zcull_per_gpc_count;
u32 max_tpc_count;
u32 gpc_count;
u32 tpc_count;
u32 ppc_count;
u32 zcb_count;
u32 pe_count_per_gpc;
u32 sm_count_per_tpc;
u32 *gpc_ppc_count;
u32 *gpc_tpc_count;
u32 *gpc_zcb_count;
u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC];
u32 gpc_mask;
u32 *gpc_tpc_mask;
u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_skip_mask;
u8 *map_tiles;
u32 map_tile_count;
u32 map_row_offset;
u32 no_of_sm;
struct sm_info *sm_to_cluster;
};
struct sm_info;
struct nvgpu_gr_config;
struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g);
void nvgpu_gr_config_deinit(struct gk20a *g, struct nvgpu_gr_config *config);
@@ -77,6 +36,7 @@ int nvgpu_gr_config_init_map_tiles(struct gk20a *g,
u32 nvgpu_gr_config_get_map_tile_count(struct nvgpu_gr_config *config,
u32 index);
u8 *nvgpu_gr_config_get_map_tiles(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_map_row_offset(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_max_gpc_count(struct nvgpu_gr_config *config);
@@ -94,6 +54,7 @@ u32 nvgpu_gr_config_get_sm_count_per_tpc(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_gpc_ppc_count(struct nvgpu_gr_config *config,
u32 gpc_index);
u32 *nvgpu_gr_config_get_gpc_tpc_count_base(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_gpc_tpc_count(struct nvgpu_gr_config *config,
u32 gpc_index);
u32 nvgpu_gr_config_get_gpc_zcb_count(struct nvgpu_gr_config *config,
@@ -101,15 +62,31 @@ u32 nvgpu_gr_config_get_gpc_zcb_count(struct nvgpu_gr_config *config,
u32 nvgpu_gr_config_get_pes_tpc_count(struct nvgpu_gr_config *config,
u32 gpc_index, u32 pes_index);
u32 *nvgpu_gr_config_get_gpc_tpc_mask_base(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_gpc_tpc_mask(struct nvgpu_gr_config *config,
u32 gpc_index);
void nvgpu_gr_config_set_gpc_tpc_mask(struct nvgpu_gr_config *config,
u32 gpc_index, u32 val);
u32 nvgpu_gr_config_get_gpc_skip_mask(struct nvgpu_gr_config *config,
u32 gpc_index);
u32 nvgpu_gr_config_get_pes_tpc_mask(struct nvgpu_gr_config *config,
u32 gpc_index, u32 pes_index);
u32 nvgpu_gr_config_get_gpc_mask(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_no_of_sm(struct nvgpu_gr_config *config);
struct sm_info *
nvgpu_gr_config_get_sm_info(struct nvgpu_gr_config *config, u32 sm_id);
void nvgpu_gr_config_set_no_of_sm(struct nvgpu_gr_config *config, u32 no_of_sm);
struct sm_info *nvgpu_gr_config_get_sm_info(struct nvgpu_gr_config *config,
u32 sm_id);
u32 nvgpu_gr_config_get_sm_info_gpc_index(struct sm_info *sm_info);
void nvgpu_gr_config_set_sm_info_gpc_index(struct sm_info *sm_info,
u32 gpc_index);
u32 nvgpu_gr_config_get_sm_info_tpc_index(struct sm_info *sm_info);
void nvgpu_gr_config_set_sm_info_tpc_index(struct sm_info *sm_info,
u32 tpc_index);
u32 nvgpu_gr_config_get_sm_info_global_tpc_index(struct sm_info *sm_info);
void nvgpu_gr_config_set_sm_info_global_tpc_index(struct sm_info *sm_info,
u32 global_tpc_index);
u32 nvgpu_gr_config_get_sm_info_sm_index(struct sm_info *sm_info);
void nvgpu_gr_config_set_sm_info_sm_index(struct sm_info *sm_info,
u32 sm_index);
#endif /* NVGPU_GR_CONFIG_H */

18
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -552,7 +552,8 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g,
{
struct gr_gk20a *gr = &g->gr;
int err = 0;
const u32 gpc_tpc_mask_size = sizeof(u32) * gr->config->max_gpc_count;
const u32 gpc_tpc_mask_size = sizeof(u32) *
nvgpu_gr_config_get_max_gpc_count(gr->config);
if (args->mask_buf_size > 0) {
size_t write_size = gpc_tpc_mask_size;
@@ -562,8 +563,9 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g,
write_size = args->mask_buf_size;
err = copy_to_user((void __user *)(uintptr_t)
args->mask_buf_addr,
gr->config->gpc_tpc_mask, write_size);
args->mask_buf_addr,
nvgpu_gr_config_get_gpc_tpc_mask_base(gr->config),
write_size);
}
if (err == 0)
@@ -815,14 +817,16 @@ static int gk20a_ctrl_vsm_mapping(struct gk20a *g,
for (i = 0; i < no_of_sm; i++) {
struct sm_info *sm_info =
nvgpu_gr_config_get_sm_info(gr->config, i);
vsms_buf[i].gpc_index = sm_info->gpc_index;
vsms_buf[i].gpc_index =
nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
if (g->ops.gr.get_nonpes_aware_tpc)
vsms_buf[i].tpc_index =
g->ops.gr.get_nonpes_aware_tpc(g,
sm_info->gpc_index,
sm_info->tpc_index);
nvgpu_gr_config_get_sm_info_gpc_index(sm_info),
nvgpu_gr_config_get_sm_info_tpc_index(sm_info));
else
vsms_buf[i].tpc_index = sm_info->tpc_index;
vsms_buf[i].tpc_index =
nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
}
err = copy_to_user((void __user *)(uintptr_t)

7
drivers/gpu/nvgpu/os/linux/sysfs.c
View File

@@ -877,11 +877,12 @@ static ssize_t tpc_fs_mask_store(struct device *dev,
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
if (!config->gpc_tpc_mask)
if (nvgpu_gr_config_get_gpc_tpc_mask_base(config) != NULL)
return -ENODEV;
if (val && val != config->gpc_tpc_mask[0] && g->ops.gr.set_gpc_tpc_mask) {
config->gpc_tpc_mask[0] = val;
if (val && val != nvgpu_gr_config_get_gpc_tpc_mask(config, 0) &&
g->ops.gr.set_gpc_tpc_mask) {
nvgpu_gr_config_set_gpc_tpc_mask(config, 0, val);
g->tpc_fs_mask_user = val;
g->ops.gr.set_gpc_tpc_mask(g, 0);