gpu: nvgpu: gv11b: MISRA 21.2 header guard fixes

MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gv11b hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.

JIRA NVGPU-1028

Change-Id: Ifceda60d2fbd33bdb5d05bf1e484819d88dedd1e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829718
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
smadhavan
2018-09-28 14:50:01 +05:30
committed by Abdul Salam
parent e4f9bf5a47
commit c657dde81e
24 changed files with 59 additions and 59 deletions

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_bus_gv11b_h_
#define _hw_bus_gv11b_h_
#ifndef NVGPU_HW_BUS_GV11B_H
#define NVGPU_HW_BUS_GV11B_H
static inline u32 bus_bar0_window_r(void)
{

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ccsr_gv11b_h_
#define _hw_ccsr_gv11b_h_
#ifndef NVGPU_HW_CCSR_GV11B_H
#define NVGPU_HW_CCSR_GV11B_H
static inline u32 ccsr_channel_inst_r(u32 i)
{

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ce_gv11b_h_
#define _hw_ce_gv11b_h_
#ifndef NVGPU_HW_CE_GV11B_H
#define NVGPU_HW_CE_GV11B_H
static inline u32 ce_intr_status_r(u32 i)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ctxsw_prog_gv11b_h_
#define _hw_ctxsw_prog_gv11b_h_
#ifndef NVGPU_HW_CTXSW_PROG_GV11B_H
#define NVGPU_HW_CTXSW_PROG_GV11B_H
static inline u32 ctxsw_prog_fecs_header_v(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_falcon_gv11b_h_
#define _hw_falcon_gv11b_h_
#ifndef NVGPU_HW_FALCON_GV11B_H
#define NVGPU_HW_FALCON_GV11B_H
static inline u32 falcon_falcon_irqsset_r(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_fb_gv11b_h_
#define _hw_fb_gv11b_h_
#ifndef NVGPU_HW_FB_GV11B_H
#define NVGPU_HW_FB_GV11B_H
static inline u32 fb_fbhub_num_active_ltcs_r(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_fifo_gv11b_h_
#define _hw_fifo_gv11b_h_
#ifndef NVGPU_HW_FIFO_GV11B_H
#define NVGPU_HW_FIFO_GV11B_H
static inline u32 fifo_userd_writeback_r(void)
{

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_flush_gv11b_h_
#define _hw_flush_gv11b_h_
#ifndef NVGPU_HW_FLUSH_GV11B_H
#define NVGPU_HW_FLUSH_GV11B_H
static inline u32 flush_l2_system_invalidate_r(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_fuse_gv11b_h_
#define _hw_fuse_gv11b_h_
#ifndef NVGPU_HW_FUSE_GV11B_H
#define NVGPU_HW_FUSE_GV11B_H
static inline u32 fuse_status_opt_gpc_r(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_gmmu_gv11b_h_
#define _hw_gmmu_gv11b_h_
#ifndef NVGPU_HW_GMMU_GV11B_H
#define NVGPU_HW_GMMU_GV11B_H
static inline u32 gmmu_new_pde_is_pte_w(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_gr_gv11b_h_
#define _hw_gr_gv11b_h_
#ifndef NVGPU_HW_GR_GV11B_H
#define NVGPU_HW_GR_GV11B_H
static inline u32 gr_intr_r(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ltc_gv11b_h_
#define _hw_ltc_gv11b_h_
#ifndef NVGPU_HW_LTC_GV11B_H
#define NVGPU_HW_LTC_GV11B_H
static inline u32 ltc_pltcg_base_v(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_mc_gv11b_h_
#define _hw_mc_gv11b_h_
#ifndef NVGPU_HW_MC_GV11B_H
#define NVGPU_HW_MC_GV11B_H
static inline u32 mc_boot_0_r(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_pbdma_gv11b_h_
#define _hw_pbdma_gv11b_h_
#ifndef NVGPU_HW_PBDMA_GV11B_H
#define NVGPU_HW_PBDMA_GV11B_H
static inline u32 pbdma_gp_entry1_r(void)
{

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_pram_gv11b_h_
#define _hw_pram_gv11b_h_
#ifndef NVGPU_HW_PRAM_GV11B_H
#define NVGPU_HW_PRAM_GV11B_H
static inline u32 pram_data032_r(u32 i)
{

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_pri_ringmaster_gv11b_h_
#define _hw_pri_ringmaster_gv11b_h_
#ifndef NVGPU_HW_PRI_RINGMASTER_GV11B_H
#define NVGPU_HW_PRI_RINGMASTER_GV11B_H
static inline u32 pri_ringmaster_command_r(void)
{

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_pri_ringstation_gpc_gv11b_h_
#define _hw_pri_ringstation_gpc_gv11b_h_
#ifndef NVGPU_HW_PRI_RINGSTATION_GPC_GV11B_H
#define NVGPU_HW_PRI_RINGSTATION_GPC_GV11B_H
static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
{

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_pri_ringstation_sys_gv11b_h_
#define _hw_pri_ringstation_sys_gv11b_h_
#ifndef NVGPU_HW_PRI_RINGSTATION_SYS_GV11B_H
#define NVGPU_HW_PRI_RINGSTATION_SYS_GV11B_H
static inline u32 pri_ringstation_sys_master_config_r(u32 i)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_proj_gv11b_h_
#define _hw_proj_gv11b_h_
#ifndef NVGPU_HW_PROJ_GV11B_H
#define NVGPU_HW_PROJ_GV11B_H
static inline u32 proj_gpc_base_v(void)
{

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_pwr_gv11b_h_
#define _hw_pwr_gv11b_h_
#ifndef NVGPU_HW_PWR_GV11B_H
#define NVGPU_HW_PWR_GV11B_H
static inline u32 pwr_falcon_irqsset_r(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_ram_gv11b_h_
#define _hw_ram_gv11b_h_
#ifndef NVGPU_HW_RAM_GV11B_H
#define NVGPU_HW_RAM_GV11B_H
static inline u32 ram_in_ramfc_s(void)
{

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@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_therm_gv11b_h_
#define _hw_therm_gv11b_h_
#ifndef NVGPU_HW_THERM_GV11B_H
#define NVGPU_HW_THERM_GV11B_H
static inline u32 therm_use_a_r(void)
{

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_timer_gv11b_h_
#define _hw_timer_gv11b_h_
#ifndef NVGPU_HW_TIMER_GV11B_H
#define NVGPU_HW_TIMER_GV11B_H
static inline u32 timer_pri_timeout_r(void)
{

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef _hw_top_gv11b_h_
#define _hw_top_gv11b_h_
#ifndef NVGPU_HW_TOP_GV11B_H
#define NVGPU_HW_TOP_GV11B_H
static inline u32 top_num_gpcs_r(void)
{