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gpu: nvgpu: use safe ops in ALIGN and ALIGN_MASK

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Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
  throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
  used.

Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.

Also, change users of ALIGN to pass unsigned types only.

JIRA NVGPU-3515
Jira NVGPU-3411

Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Nitin Kumbhar
2019-05-31 15:35:42 +05:30
committed by mobile promotions
parent 7ee75980cc
commit c69c5a7a60
12 changed files with 77 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c
View File

@@ -104,14 +104,14 @@ int nvgpu_acr_lsf_fecs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img)
}
p_img->desc->bootloader_start_offset = fecs->boot.offset;
p_img->desc->bootloader_size = ALIGN(fecs->boot.size, 256);
p_img->desc->bootloader_size = ALIGN(fecs->boot.size, 256U);
p_img->desc->bootloader_imem_offset = fecs->boot_imem_offset;
p_img->desc->bootloader_entry_point = fecs->boot_entry;
p_img->desc->image_size = ALIGN(fecs->boot.size, 256) +
ALIGN(fecs->code.size, 256) + ALIGN(fecs->data.size, 256);
p_img->desc->app_size = ALIGN(fecs->code.size, 256) +
ALIGN(fecs->data.size, 256);
p_img->desc->image_size = ALIGN(fecs->boot.size, 256U) +
ALIGN(fecs->code.size, 256U) + ALIGN(fecs->data.size, 256U);
p_img->desc->app_size = ALIGN(fecs->code.size, 256U) +
ALIGN(fecs->data.size, 256U);
p_img->desc->app_start_offset = fecs->code.offset;
p_img->desc->app_imem_offset = 0;
p_img->desc->app_imem_entry = 0;
@@ -173,27 +173,28 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img)
p_img->desc->bootloader_start_offset =
0;
p_img->desc->bootloader_size = ALIGN(gpccs->boot.size, 256);
p_img->desc->bootloader_size = ALIGN(gpccs->boot.size, 256U);
p_img->desc->bootloader_imem_offset = gpccs->boot_imem_offset;
p_img->desc->bootloader_entry_point = gpccs->boot_entry;
p_img->desc->image_size = ALIGN(gpccs->boot.size, 256) +
ALIGN(gpccs->code.size, 256) + ALIGN(gpccs->data.size, 256);
p_img->desc->image_size = ALIGN(gpccs->boot.size, 256U) +
ALIGN(gpccs->code.size, 256U) + ALIGN(gpccs->data.size, 256U);
p_img->desc->app_size =
ALIGN(gpccs->code.size, 256) + ALIGN(gpccs->data.size, 256);
ALIGN(gpccs->code.size, 256U) + ALIGN(gpccs->data.size, 256U);
p_img->desc->app_start_offset = p_img->desc->bootloader_size;
p_img->desc->app_imem_offset = 0;
p_img->desc->app_imem_entry = 0;
p_img->desc->app_dmem_offset = 0;
p_img->desc->app_resident_code_offset = 0;
p_img->desc->app_resident_code_size = ALIGN(gpccs->code.size, 256);
p_img->desc->app_resident_data_offset = ALIGN(gpccs->data.offset, 256) -
ALIGN(gpccs->code.offset, 256);
p_img->desc->app_resident_data_size = ALIGN(gpccs->data.size, 256);
p_img->desc->app_resident_code_size = ALIGN(gpccs->code.size, 256U);
p_img->desc->app_resident_data_offset =
ALIGN(gpccs->data.offset, 256U) -
ALIGN(gpccs->code.offset, 256U);
p_img->desc->app_resident_data_size = ALIGN(gpccs->data.size, 256U);
p_img->data = (u32 *)
((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon) +
gpccs->boot.offset);
p_img->data_size = ALIGN(p_img->desc->image_size, 256);
p_img->data_size = ALIGN(p_img->desc->image_size, 256U);
p_img->fw_ver = NULL;
p_img->header = NULL;
p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;

31
drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c
View File

@@ -128,14 +128,14 @@ int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
}
p_img->desc->bootloader_start_offset = fecs->boot.offset;
p_img->desc->bootloader_size = ALIGN(fecs->boot.size, 256);
p_img->desc->bootloader_size = ALIGN(fecs->boot.size, 256U);
p_img->desc->bootloader_imem_offset = fecs->boot_imem_offset;
p_img->desc->bootloader_entry_point = fecs->boot_entry;
p_img->desc->image_size = ALIGN(fecs->boot.size, 256) +
ALIGN(fecs->code.size, 256) + ALIGN(fecs->data.size, 256);
p_img->desc->app_size = ALIGN(fecs->code.size, 256) +
ALIGN(fecs->data.size, 256);
p_img->desc->image_size = ALIGN(fecs->boot.size, 256U) +
ALIGN(fecs->code.size, 256U) + ALIGN(fecs->data.size, 256U);
p_img->desc->app_size = ALIGN(fecs->code.size, 256U) +
ALIGN(fecs->data.size, 256U);
p_img->desc->app_start_offset = fecs->code.offset;
p_img->desc->app_imem_offset = 0;
p_img->desc->app_imem_entry = 0;
@@ -217,27 +217,28 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
}
p_img->desc->bootloader_start_offset = 0;
p_img->desc->bootloader_size = ALIGN(gpccs->boot.size, 256);
p_img->desc->bootloader_size = ALIGN(gpccs->boot.size, 256U);
p_img->desc->bootloader_imem_offset = gpccs->boot_imem_offset;
p_img->desc->bootloader_entry_point = gpccs->boot_entry;
p_img->desc->image_size = ALIGN(gpccs->boot.size, 256) +
ALIGN(gpccs->code.size, 256) + ALIGN(gpccs->data.size, 256);
p_img->desc->app_size = ALIGN(gpccs->code.size, 256)
+ ALIGN(gpccs->data.size, 256);
p_img->desc->image_size = ALIGN(gpccs->boot.size, 256U) +
ALIGN(gpccs->code.size, 256U) + ALIGN(gpccs->data.size, 256U);
p_img->desc->app_size = ALIGN(gpccs->code.size, 256U)
+ ALIGN(gpccs->data.size, 256U);
p_img->desc->app_start_offset = p_img->desc->bootloader_size;
p_img->desc->app_imem_offset = 0;
p_img->desc->app_imem_entry = 0;
p_img->desc->app_dmem_offset = 0;
p_img->desc->app_resident_code_offset = 0;
p_img->desc->app_resident_code_size = ALIGN(gpccs->code.size, 256);
p_img->desc->app_resident_data_offset = ALIGN(gpccs->data.offset, 256) -
ALIGN(gpccs->code.offset, 256);
p_img->desc->app_resident_data_size = ALIGN(gpccs->data.size, 256);
p_img->desc->app_resident_code_size = ALIGN(gpccs->code.size, 256U);
p_img->desc->app_resident_data_offset =
ALIGN(gpccs->data.offset, 256U) -
ALIGN(gpccs->code.offset, 256U);
p_img->desc->app_resident_data_size = ALIGN(gpccs->data.size, 256U);
p_img->data = (u32 *)
((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon) +
gpccs->boot.offset);
p_img->data_size = ALIGN(p_img->desc->image_size, 256);
p_img->data_size = ALIGN(p_img->desc->image_size, 256U);
p_img->fw_ver = NULL;
p_img->header = NULL;
p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc;

3
drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c
View File

@@ -116,7 +116,8 @@ static int engine_mem_queue_rewind(struct nvgpu_falcon *flcn,
queue->flcn_id, queue->id);
goto exit;
} else {
queue->position += ALIGN(cmd.hdr.size, QUEUE_ALIGNMENT);
queue->position += nvgpu_safe_cast_u32_to_u8(
ALIGN(U32(cmd.hdr.size), QUEUE_ALIGNMENT));
nvgpu_log_info(g, "flcn-%d queue-%d, rewinded",
queue->flcn_id, queue->id);
}

6
drivers/gpu/nvgpu/common/gr/hwpm_map.c
View File

@@ -299,7 +299,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
}
}
*offset = ALIGN(*offset, 256);
*offset = ALIGN(*offset, 256U);
}
return 0;
}
@@ -434,7 +434,7 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
goto cleanup;
}
offset = ALIGN(offset, 256);
offset = ALIGN(offset, 256U);
/* Add entries from _LIST_nv_perf_fbp_ctx_regs */
if (add_ctxsw_buffer_map_entries_subunits(map,
@@ -484,7 +484,7 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
goto cleanup;
}
offset = ALIGN(offset, 256);
offset = ALIGN(offset, 256U);
/* Add GPC entries */
if (add_ctxsw_buffer_map_entries_gpcs(g, map, &count, &offset,

2
drivers/gpu/nvgpu/common/sec2/ipc/sec2_msg.c
View File

@@ -148,7 +148,7 @@ static int sec2_process_init_msg(struct nvgpu_sec2 *sec2,
goto exit;
}
tail += ALIGN(msg->hdr.size, PMU_DMEM_ALIGNMENT);
tail += ALIGN(U32(msg->hdr.size), PMU_DMEM_ALIGNMENT);
g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_SET);
sec2_init = &msg->msg.init.sec2_init;

2
drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c
View File

@@ -249,7 +249,7 @@ int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn,
nvgpu_writel(g, base_addr + falcon_falcon_dmemd_r(port), data);
}
size = ALIGN(size, 4);
size = ALIGN(size, 4U);
data = nvgpu_readl(g,
base_addr + falcon_falcon_dmemc_r(port)) & addr_mask;
if (data != ((dst + size) & addr_mask)) {

2
drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c
View File

@@ -81,7 +81,7 @@ int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g,
}
/* aligned to next 256 byte */
offset_in_segment = ALIGN(offset_in_segment, 256);
offset_in_segment = ALIGN(offset_in_segment, 256U);
nvgpu_log(g, gpu_dbg_info | gpu_dbg_gpu_dbg,
"egpc etpc offset_in_segment 0x%#08x",

2
drivers/gpu/nvgpu/hal/gr/hwpm_map/hwpm_map_gv100.c
View File

@@ -28,7 +28,7 @@
void gv100_gr_hwpm_map_align_regs_perf_pma(u32 *offset)
{
*offset = ALIGN(*offset, 256);
*offset = ALIGN(*offset, 256U);
}
u32 gv100_gr_hwpm_map_get_active_fbpa_mask(struct gk20a *g)

4
drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
View File

@@ -289,7 +289,7 @@ u32 gp10b_gr_init_get_global_attr_cb_size(struct gk20a *g, u32 tpc_count,
gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(),
max_tpc)));
size = ALIGN(size, 128);
size = ALIGN(size, 128U);
return size;
}
@@ -564,7 +564,7 @@ u32 gp10b_gr_init_get_ctx_attrib_cb_size(struct gk20a *g, u32 betacb_size,
gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(),
max_tpc));
return ALIGN(size, 128);
return ALIGN(size, 128U);
}
void gp10b_gr_init_commit_cbes_reserve(struct gk20a *g,

2
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c
View File

@@ -649,7 +649,7 @@ u32 gv11b_gr_init_get_global_attr_cb_size(struct gk20a *g, u32 tpc_count,
gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(),
max_tpc)));
size = ALIGN(size, 128);
size = ALIGN(size, 128U);
return size;
}

46
drivers/gpu/nvgpu/include/nvgpu/posix/utils.h
View File

@@ -98,23 +98,37 @@
#define roundup(x, y) round_up(x, y)
#define round_down(x, y) ((x) & ~round_mask(x, y))
#define ALIGN_MASK(x, mask) \
({ \
typeof(x) ret; \
typeof(x) sum = (x) + (mask); \
\
if ((sum >= (x)) && (sum >= (mask))) { \
ret = sum & ~(mask); \
} else { \
ret = (typeof(x))~(typeof(x))0 & ~(mask); \
} \
ret; \
})
#define IS_UNSIGNED_TYPE(x) \
(__builtin_types_compatible_p(typeof(x), unsigned int) || \
__builtin_types_compatible_p(typeof(x), unsigned long) || \
__builtin_types_compatible_p(typeof(x), unsigned long long))
#define IS_UNSIGNED_LONG_TYPE(x) \
(__builtin_types_compatible_p(typeof(x), unsigned long) || \
__builtin_types_compatible_p(typeof(x), unsigned long long))
#define ALIGN_MASK(x, mask) \
__builtin_choose_expr( \
(IS_UNSIGNED_TYPE(x) && IS_UNSIGNED_TYPE(mask)), \
__builtin_choose_expr( \
IS_UNSIGNED_LONG_TYPE(x), \
(nvgpu_safe_add_u64((x), (mask)) & ~(mask)), \
(nvgpu_safe_add_u32((x), (mask)) & ~(mask))), \
/* Results in build error. Make x/mask type unsigned */ \
(void)0)
#define ALIGN(x, a) \
__builtin_choose_expr( \
(IS_UNSIGNED_TYPE(x) && IS_UNSIGNED_TYPE(a)), \
__builtin_choose_expr( \
IS_UNSIGNED_LONG_TYPE(x), \
ALIGN_MASK((x), \
(nvgpu_safe_sub_u64((typeof(x))(a), 1))), \
ALIGN_MASK((x), \
(nvgpu_safe_sub_u32((typeof(x))(a), 1)))), \
/* Results in build error. Make x/a type unsigned */ \
(void)0)
#define ALIGN(x, a) ALIGN_MASK(x, \
(a) > (typeof(a))0 ? \
(typeof(x))(a) - 1U : \
(typeof(x))0)
#define PAGE_ALIGN(x) ALIGN(x, PAGE_SIZE)
#define HZ_TO_KHZ(x) ((x) / KHZ)

6
drivers/gpu/nvgpu/os/posix/bitmap.c
View File

@@ -170,8 +170,10 @@ unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
while (start + nr <= size) {
start = find_next_zero_bit(map, size, start);
start = ALIGN_MASK(start + align_offset, align_mask) -
align_offset;
start = nvgpu_safe_sub_u64(
ALIGN_MASK(nvgpu_safe_add_u64(start, align_offset),
align_mask),
align_offset);
/*
* Not enough space left to satisfy the requested area.