From c6fc301a9bc836eb5bd275eeedbf73782ca26829 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Mon, 10 Dec 2018 13:49:18 +0530 Subject: [PATCH] gpu: nvgpu: update FECS falcon base addr init FECS falcon base address was being set without invoking hal api. Remove FALCON_FECS_BASE. This patch defines gpu_ops.gr.fecs_falcon_base_addr hal api to get this base address. JIRA NVGPU-1587 Change-Id: I9c8e60be4ee81a154020c982893725a12ebb72ef Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/1969430 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c | 2 +- drivers/gpu/nvgpu/common/falcon/falcon_gp106.c | 2 +- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 5 +++++ drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 1 + drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 + drivers/gpu/nvgpu/gp106/gr_gp106.c | 5 +++++ drivers/gpu/nvgpu/gp106/gr_gp106.h | 1 + drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/falcon.h | 1 - drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 + drivers/gpu/nvgpu/tu104/hal_tu104.c | 3 +++ 14 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c b/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c index 805905839..d02d40959 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c @@ -728,7 +728,7 @@ int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn) flcn->is_interrupt_enabled = true; break; case FALCON_ID_FECS: - flcn->flcn_base = FALCON_FECS_BASE; + flcn->flcn_base = g->ops.gr.fecs_falcon_base_addr(); flcn->is_falcon_supported = true; flcn->is_interrupt_enabled = false; break; diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c b/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c index 2abdc0e6d..cc85f8378 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c @@ -71,7 +71,7 @@ int gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn) flcn->is_interrupt_enabled = false; break; case FALCON_ID_FECS: - flcn->flcn_base = FALCON_FECS_BASE; + flcn->flcn_base = g->ops.gr.fecs_falcon_base_addr(); flcn->is_falcon_supported = true; flcn->is_interrupt_enabled = false; break; diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index ccb4fd93d..b3e058f51 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -8681,3 +8681,8 @@ u32 gk20a_gr_get_fecs_ctx_state_store_major_rev_id(struct gk20a *g) { return nvgpu_readl(g, gr_fecs_ctx_state_store_major_rev_id_r()); } + +u32 gr_gk20a_fecs_falcon_base_addr(void) +{ + return gr_fecs_irqsset_r(); +} diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index db740ec5c..339d3b876 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -797,4 +797,5 @@ int gk20a_gr_alloc_ctx_buffer(struct gk20a *g, void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr); u32 gk20a_gr_get_fecs_ctx_state_store_major_rev_id(struct gk20a *g); +u32 gr_gk20a_fecs_falcon_base_addr(void); #endif /*__GR_GK20A_H__*/ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 2447eee0c..59c5f7d85 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -233,6 +233,7 @@ static const struct gpu_ops gm20b_ops = { .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, .init_fs_state = gr_gm20b_init_fs_state, .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, + .fecs_falcon_base_addr = gr_gk20a_fecs_falcon_base_addr, .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, .set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask, diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index bcbd3c17c..1b1b576e7 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c @@ -256,3 +256,8 @@ fail_free_preempt: fail: return err; } + +u32 gr_gp106_fecs_falcon_base_addr(void) +{ + return gr_fecs_irqsset_r(); +} diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.h b/drivers/gpu/nvgpu/gp106/gr_gp106.h index 20e13e9ed..2c8445d18 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.h @@ -40,5 +40,6 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, struct vm_gk20a *vm, u32 class, u32 graphics_preempt_mode, u32 compute_preempt_mode); +u32 gr_gp106_fecs_falcon_base_addr(void); #endif /* NVGPU_GR_GP106_H */ diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index ebf21125c..c1aa6518b 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -297,6 +297,7 @@ static const struct gpu_ops gp106_ops = { .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, .init_fs_state = gr_gp10b_init_fs_state, .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, + .fecs_falcon_base_addr = gr_gp106_fecs_falcon_base_addr, .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 3cad32af0..ddb2ee323 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -252,6 +252,7 @@ static const struct gpu_ops gp10b_ops = { .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, .init_fs_state = gr_gp10b_init_fs_state, .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, + .fecs_falcon_base_addr = gr_gk20a_fecs_falcon_base_addr, .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 604acd5a6..f1df876f6 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -81,6 +81,7 @@ #include "gp106/sec2_gp106.h" #include "gp106/bios_gp106.h" +#include "gp106/gr_gp106.h" #include "gp10b/gr_gp10b.h" #include "gp10b/ce_gp10b.h" @@ -354,6 +355,7 @@ static const struct gpu_ops gv100_ops = { .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, .init_fs_state = gr_gv11b_init_fs_state, .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, + .fecs_falcon_base_addr = gr_gp106_fecs_falcon_base_addr, .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index daf266da0..08e99e2c9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -305,6 +305,7 @@ static const struct gpu_ops gv11b_ops = { .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, .init_fs_state = gr_gv11b_init_fs_state, .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, + .fecs_falcon_base_addr = gr_gk20a_fecs_falcon_base_addr, .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 5956dbf0e..4217759b5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h @@ -42,7 +42,6 @@ /* * Falcon Base address Defines */ -#define FALCON_FECS_BASE 0x00409000U #define FALCON_GPCCS_BASE 0x0041a000U /* Falcon Register index */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 28f68e8fc..fa752d025 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -622,6 +622,7 @@ struct gpu_ops { void (*dump_ctxsw_stats)(struct gk20a *g, struct nvgpu_mem *ctx_mem); } ctxsw_prog; + u32 (*fecs_falcon_base_addr)(void); } gr; struct { void (*init_hw)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 2c974953c..457f4e707 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -88,6 +88,8 @@ #include "gp106/sec2_gp106.h" #include "gp106/bios_gp106.h" +#include "gp106/gr_gp106.h" + #include "gp10b/gr_gp10b.h" #include "gp10b/ce_gp10b.h" #include "gp10b/fifo_gp10b.h" @@ -368,6 +370,7 @@ static const struct gpu_ops tu104_ops = { .get_sm_dsm_perf_ctrl_regs = gr_tu104_get_sm_dsm_perf_ctrl_regs, .init_fs_state = gr_gv11b_init_fs_state, .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, + .fecs_falcon_base_addr = gr_gp106_fecs_falcon_base_addr, .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask,