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gpu: nvgpu: Remove alloc_inst_block from mm HAL
The alloc_insty_block() function in the MM HAL is not a HAL. It does not abstract any HW accesses; instead it just wraps a dma allocation. As such remove it from the HAL and move the single gk20a implementation to common/mm/mm.c as nvgpu_alloc_inst_block(). JIRA NVGPU-2042 Change-Id: I0a586800a11cd230ca43b85f94a35de107f5d1e1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109049 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -24,6 +24,7 @@
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#include <trace/events/gk20a.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/semaphore.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/kmem.h>
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@@ -2503,7 +2504,7 @@ int nvgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch)
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nvgpu_log_fn(g, " ");
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err = g->ops.mm.alloc_inst_block(g, &ch->inst_block);
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err = nvgpu_alloc_inst_block(g, &ch->inst_block);
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if (err != 0) {
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return err;
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}
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@@ -202,7 +202,7 @@ static int nvgpu_gr_falcon_init_ctxsw_ucode_vaspace(struct gk20a *g,
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struct nvgpu_ctxsw_ucode_info *ucode_info = &falcon->ctxsw_ucode_info;
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int err;
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err = g->ops.mm.alloc_inst_block(g, &ucode_info->inst_blk_desc);
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err = nvgpu_alloc_inst_block(g, &ucode_info->inst_blk_desc);
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if (err != 0) {
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return err;
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}
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@@ -168,6 +168,22 @@ void nvgpu_free_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block)
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}
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}
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int nvgpu_alloc_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block)
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{
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int err;
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nvgpu_log_fn(g, " ");
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err = nvgpu_dma_alloc(g, g->ops.ramin.alloc_size(), inst_block);
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if (err != 0) {
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nvgpu_err(g, "%s: memory allocation failed", __func__);
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return err;
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}
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nvgpu_log_fn(g, "done");
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return 0;
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}
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static int nvgpu_alloc_sysmem_flush(struct gk20a *g)
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{
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return nvgpu_dma_alloc_sys(g, SZ_4K, &g->mm.sysmem_flush);
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@@ -269,7 +285,7 @@ static int nvgpu_init_system_vm(struct mm_gk20a *mm)
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return -ENOMEM;
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}
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err = g->ops.mm.alloc_inst_block(g, inst_block);
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err = nvgpu_alloc_inst_block(g, inst_block);
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if (err != 0) {
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goto clean_up_vm;
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}
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@@ -288,7 +304,7 @@ static int nvgpu_init_hwpm(struct mm_gk20a *mm)
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struct gk20a *g = gk20a_from_mm(mm);
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struct nvgpu_mem *inst_block = &mm->hwpm.inst_block;
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err = g->ops.mm.alloc_inst_block(g, inst_block);
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err = nvgpu_alloc_inst_block(g, inst_block);
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if (err != 0) {
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return err;
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}
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@@ -411,7 +427,7 @@ static int nvgpu_init_bar1_vm(struct mm_gk20a *mm)
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return -ENOMEM;
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}
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err = g->ops.mm.alloc_inst_block(g, inst_block);
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err = nvgpu_alloc_inst_block(g, inst_block);
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if (err != 0) {
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goto clean_up_vm;
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}
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@@ -444,7 +460,7 @@ static int nvgpu_init_engine_ucode_vm(struct gk20a *g,
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}
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/* allocate instance mem for engine ucode */
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err = g->ops.mm.alloc_inst_block(g, inst_block);
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err = nvgpu_alloc_inst_block(g, inst_block);
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if (err != 0) {
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goto clean_up_va;
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}
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@@ -20,6 +20,7 @@
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/mm.h>
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#include <nvgpu/sizes.h>
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#include <nvgpu/perfbuf.h>
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#include <nvgpu/gk20a.h>
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@@ -35,7 +36,7 @@ int nvgpu_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size)
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return err;
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}
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err = g->ops.mm.alloc_inst_block(g, &mm->perfbuf.inst_block);
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err = nvgpu_alloc_inst_block(g, &mm->perfbuf.inst_block);
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if (err != 0) {
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return err;
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}
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