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gpu: nvgpu: leave LTC evicted_cb intr disabled

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The evicted_cb interrupt is occurring more frequently than
expected and has no SW action that can be taken to avoid it.

This interrupt is being disabled which is consistent with
the HW POR value and the setting used on previous chips.

Bug 3464717

Signed-off-by: Chris Johnson <cwj@nvidia.com>
Change-Id: Ibc87f4bf287eeef158e46126a5e7f8a3cc575390
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2654678
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Chris Johnson
2022-01-14 09:44:59 -08:00
committed by mobile promotions
parent 8834d598e4
commit c78998f99b
2 changed files with 6 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
View File

@@ -64,9 +64,12 @@ static void ga10b_ltc_intr1_configure(struct gk20a *g)
* EVICTED_CB - indicates that a CB was demoted. * EVICTED_CB - indicates that a CB was demoted.
* Normally this should not happen because the CBs should be flushed * Normally this should not happen because the CBs should be flushed
* during context switch and/or invalidated when no longer used. * during context switch and/or invalidated when no longer used.
*
* Note: this occurs more frequently than expected, so is being left
* disabled as on previous chips and consistent with HW POR value.
*/ */
reg = set_field(reg, ltc_ltcs_ltss_intr_en_evicted_cb_m(), reg = set_field(reg, ltc_ltcs_ltss_intr_en_evicted_cb_m(),
ltc_ltcs_ltss_intr_en_evicted_cb_enabled_f()); ltc_ltcs_ltss_intr_en_evicted_cb_disabled_f());
/* /*
* ILLEGAL_ATOMIC - unsupported atomic op and/or size received. * ILLEGAL_ATOMIC - unsupported atomic op and/or size received.

3
drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ltc_ga10b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -154,6 +154,7 @@
#define ltc_ltcs_ltss_intr_evicted_cb_reset_f() (0x10U) #define ltc_ltcs_ltss_intr_evicted_cb_reset_f() (0x10U)
#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U) #define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U)
#define ltc_ltcs_ltss_intr_en_evicted_cb_enabled_f() (0x100000U) #define ltc_ltcs_ltss_intr_en_evicted_cb_enabled_f() (0x100000U)
#define ltc_ltcs_ltss_intr_en_evicted_cb_disabled_f() (0x0U)
#define ltc_ltcs_ltss_intr_illegal_compstat_m() (U32(0x1U) << 5U) #define ltc_ltcs_ltss_intr_illegal_compstat_m() (U32(0x1U) << 5U)
#define ltc_ltcs_ltss_intr_illegal_compstat_reset_f() (0x20U) #define ltc_ltcs_ltss_intr_illegal_compstat_reset_f() (0x20U)
#define ltc_ltcs_ltss_intr_en_illegal_compstat_m() (U32(0x1U) << 21U) #define ltc_ltcs_ltss_intr_en_illegal_compstat_m() (U32(0x1U) << 21U)