gpu: nvgpu: unit: update bvec tests for common.fuse unit

Patch adds bvec tests for below APIs.
- gops_fuse.fuse_status_opt_tpc_gpc

Jira NVGPU-6410

Change-Id: I62a2f9b2933938a5b8b2493e9bea19367f136bbd
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2542729
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2552305
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

userspace/units/fuse/nvgpu-fuse-gm20b.c

@@ -32,7 +32,6 @@
 #include "nvgpu-fuse-gm20b.h"
 
 /* register definitions for this block */
-#define GM20B_FUSE_REG_BASE			0x00021000U
 #define GM20B_FUSE_OPT_SEC_DEBUG_EN		(GM20B_FUSE_REG_BASE+0x218U)
 #define GM20B_FUSE_STATUS_OPT_PRIV_SEC_EN	(GM20B_FUSE_REG_BASE+0x434U)
 #define GM20B_FUSE_CTRL_OPT_TPC_GPC		(GM20B_FUSE_REG_BASE+0x838U)
@@ -42,7 +41,6 @@
 #define GM20B_FUSE_STATUS_OPT_FBP		(GM20B_FUSE_REG_BASE+0xD38U)
 #define GM20B_FUSE_STATUS_OPT_ROP_L2_FBP	(GM20B_FUSE_REG_BASE+0xD70U)
 #define GM20B_MAX_FBPS_COUNT			32U
-#define GM20B_MAX_GPC_COUNT			32U
 
 /* for common init args */
 struct fuse_test_args gm20b_init_args = {
@@ -255,6 +253,7 @@ int test_fuse_gm20b_basic_fuses(struct unit_module *m,
 					set*i);
 
 		}
+
 		for (i = 0; i < GM20B_MAX_GPC_COUNT; i++) {
 			val = g->ops.fuse.fuse_status_opt_tpc_gpc(g, i);
 			if (val != (set*i)) {
@@ -291,6 +290,57 @@ int test_fuse_gm20b_basic_fuses(struct unit_module *m,
 	return ret;
 }
 
+int test_fuse_gm20b_basic_fuses_bvec(struct unit_module *m,
+				struct gk20a *g, void *__args)
+{
+	int ret = UNIT_SUCCESS;
+	u32 set, val, i;
+
+/* GPC in range */
+	i = 0;
+	set = 0;
+	nvgpu_posix_io_writel_reg_space(g, GM20B_FUSE_STATUS_OPT_TPC_GPC+(i*4U),
+				set*i);
+	val = g->ops.fuse.fuse_status_opt_tpc_gpc(g, i);
+	if (val != (set*i)) {
+		unit_err(m, "%s TPC STATUS incorrect for gpc %u %u != %u\n",
+			__func__, i, val, set*i);
+		ret = UNIT_FAIL;
+	}
+
+/* GPC in range */
+	i = GM20B_MAX_GPC_COUNT - 1;
+	set = 4;
+	nvgpu_posix_io_writel_reg_space(g, GM20B_FUSE_STATUS_OPT_TPC_GPC+(i*4U),
+				set*i);
+	val = g->ops.fuse.fuse_status_opt_tpc_gpc(g, i);
+	if (val != (set*i)) {
+		unit_err(m, "%s TPC STATUS incorrect for gpc %u %u != %u\n",
+			__func__, i, val, set*i);
+		ret = UNIT_FAIL;
+	}
+
+/* GPC is equal to MAX */
+	i = GM20B_MAX_GPC_COUNT;
+	val = EXPECT_BUG(g->ops.fuse.fuse_status_opt_tpc_gpc(g, i));
+	if (val == 0) {
+		unit_err(m, "%s TPC STATUS incorrect for gpc %u %u != %u\n",
+			__func__, i, val, set*i);
+		ret = UNIT_FAIL;
+	}
+
+/* GPC is more than MAX */
+	i = GM20B_MAX_GPC_COUNT + 1;
+	val = EXPECT_BUG(g->ops.fuse.fuse_status_opt_tpc_gpc(g, i));
+	if (val == 0) {
+		unit_err(m, "%s TPC STATUS incorrect for gpc %u %u != %u\n",
+			__func__, i, val, set*i);
+		ret = UNIT_FAIL;
+	}
+
+	return ret;
+}
+
 #ifdef CONFIG_NVGPU_SIM
 /* Verify when FMODEL is enabled, fuse module reports non-secure */
 int test_fuse_gm20b_check_fmodel(struct unit_module *m,

userspace/units/fuse/nvgpu-fuse-gm20b.h

@@ -159,6 +159,31 @@ int test_fuse_gm20b_check_non_sec(struct unit_module *m,
 int test_fuse_gm20b_basic_fuses(struct unit_module *m,
 				struct gk20a *g, void *__args);
 
+/**
+ * Test specification for: test_fuse_gm20b_basic_fuses_bvec
+ *
+ * Description:  Verify fuse reads for basic value-return APIs.
+ *
+ * Test Type: BVEC
+ *
+ * Targets: gops_fuse.fuse_status_opt_tpc_gpc,
+ *
+ * Equivalence classes:
+ * - Valid : {0, gr->config->max_gpc_count - 1}
+ * - Invalid : {gr->config->max_gpc_count, U32_MAX}
+ *
+ * Input: test_fuse_device_common_init() must be called for this GPU.
+ *
+ * Steps:
+ * - For each fuse API that returns the value of the fuse, do the following:
+ *   - Read values for valid/invalid GPCs.
+ *   - Verify the correct value/error is returned.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_fuse_gm20b_basic_fuses_bvec(struct unit_module *m,
+				struct gk20a *g, void *__args);
 #ifdef CONFIG_NVGPU_SIM
 int test_fuse_gm20b_check_fmodel(struct unit_module *m,
 				 struct gk20a *g, void *__args);

userspace/units/fuse/nvgpu-fuse-priv.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -34,4 +34,7 @@ struct fuse_test_args {
 	u32 sec_fuse_addr;
 };
 
+#define GM20B_FUSE_REG_BASE			0x00021000U
+#define GM20B_TOP_NUM_GPCS			(GM20B_FUSE_REG_BASE+0x1430U)
+#define GM20B_MAX_GPC_COUNT                     24U
 #endif /* __UNIT_NVGPU_FUSE_PRIV_H__ */

userspace/units/fuse/nvgpu-fuse.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,11 +27,13 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/hal_init.h>
 #include <nvgpu/enabled.h>
+#include <common/gr/gr_priv.h>
 
 #include "nvgpu-fuse.h"
 #include "nvgpu-fuse-priv.h"
 #include "nvgpu-fuse-gp10b.h"
 #include "nvgpu-fuse-gm20b.h"
+#include "common/gr/gr_config_priv.h"
 #ifdef CONFIG_NVGPU_DGPU
 #include "nvgpu-fuse-tu104.h"
 #endif
@@ -101,9 +103,11 @@ int test_fuse_device_common_init(struct unit_module *m,
 	int ret = UNIT_SUCCESS;
 	int result;
 	struct fuse_test_args *args = (struct fuse_test_args *)__args;
+	struct nvgpu_gr gr = {0};
+	struct nvgpu_gr_config config = {0};
 
 	/* Create fuse register space */
-	if (nvgpu_posix_io_add_reg_space(g, args->fuse_base_addr, 0xfff) != 0) {
+	if (nvgpu_posix_io_add_reg_space(g, args->fuse_base_addr, 0x1fff) != 0) {
 		unit_err(m, "%s: failed to create register space\n",
 			 __func__);
 		return UNIT_FAIL;
@@ -119,6 +123,8 @@ int test_fuse_device_common_init(struct unit_module *m,
 	g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
 #endif
 
+	g->gr = &gr;
+	gr.config = &config;
 	nvgpu_posix_io_writel_reg_space(g, args->sec_fuse_addr, 0x0);
 
 	result = nvgpu_init_hal(g);
@@ -129,6 +135,8 @@ int test_fuse_device_common_init(struct unit_module *m,
 	}
 
 	g->ops.fuse.read_gcplex_config_fuse = read_gcplex_config_fuse_pass;
+	nvgpu_posix_io_writel_reg_space(g, GM20B_TOP_NUM_GPCS,
+		GM20B_MAX_GPC_COUNT);
 
 	return ret;
 }
@@ -186,6 +194,7 @@ struct unit_module_test fuse_tests[] = {
 		  0),
 #endif
 	UNIT_TEST(fuse_gm20b_basic_fuses, test_fuse_gm20b_basic_fuses, NULL, 0),
+	UNIT_TEST(test_fuse_gm20b_basic_fuses_bvec, test_fuse_gm20b_basic_fuses_bvec, NULL, 0),
 #ifdef CONFIG_NVGPU_SIM
 	UNIT_TEST(fuse_gm20b_check_fmodel, test_fuse_gm20b_check_fmodel, NULL, 0),
 #endif