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gpu: nvgpu: disable VFE frequency margin request
Disabled VFE frequency margin request to PMU as TU104 don't support this feature currently. Bug 200499055 Change-Id: I8e217cae9a0cbb6f388fb3376efc22f6e40e5c89 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2034728 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -476,7 +476,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq
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u32 max_clkmhz;
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u16 max_ratio;
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struct clk_set_info *p0_info;
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u32 vmin_uv = 0, vmargin_uv = 0U, fmargin_mhz = 0U;
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u32 vmin_uv = 0, vmargin_uv = 0U;
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(void) memset(&change_input, 0,
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sizeof(struct ctrl_perf_change_seq_change_input));
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@@ -605,13 +605,6 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq
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change_input.flags = (u32)CTRL_PERF_CHANGE_SEQ_CHANGE_FORCE;
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change_input.vf_points_cache_counter = 0xFFFFFFFFU;
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status = nvgpu_vfe_get_freq_margin_limit(g, &fmargin_mhz);
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if (status != 0) {
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nvgpu_err(g, "Failed to fetch Fmargin status=0x%x", status);
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return status;
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}
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gpcclk_clkmhz += fmargin_mhz;
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status = clk_domain_freq_to_volt(g, gpcclk_domain,
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&gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC);
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