gpu: nvgpu: disable VFE frequency margin request

Disabled VFE frequency margin request to PMU as TU104 don't support
this feature currently. 

Bug 200499055

Change-Id: I8e217cae9a0cbb6f388fb3376efc22f6e40e5c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034728
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-03-07 14:46:25 +05:30
committed by mobile promotions
parent 67caad40e9
commit c7ce4a4465

View File

@@ -476,7 +476,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq
u32 max_clkmhz;
u16 max_ratio;
struct clk_set_info *p0_info;
u32 vmin_uv = 0, vmargin_uv = 0U, fmargin_mhz = 0U;
u32 vmin_uv = 0, vmargin_uv = 0U;
(void) memset(&change_input, 0,
sizeof(struct ctrl_perf_change_seq_change_input));
@@ -605,13 +605,6 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq
change_input.flags = (u32)CTRL_PERF_CHANGE_SEQ_CHANGE_FORCE;
change_input.vf_points_cache_counter = 0xFFFFFFFFU;
status = nvgpu_vfe_get_freq_margin_limit(g, &fmargin_mhz);
if (status != 0) {
nvgpu_err(g, "Failed to fetch Fmargin status=0x%x", status);
return status;
}
gpcclk_clkmhz += fmargin_mhz;
status = clk_domain_freq_to_volt(g, gpcclk_domain,
&gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC);