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gpu: nvgpu: remove usage of CONFIG_NVGPU_NEXT

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The CONFIG_NVGPU_NEXT config is no longer required now that ga10b and
ga100 sources have been collapsed. However, the ga100, ga10b sources
are not safety certified, so mark them as NON_FUSA by replacing
CONFIG_NVGPU_NEXT with CONFIG_NVGPU_NON_FUSA.

Move CONFIG_NVGPU_MIG to Makefile.linux.config and enable MIG support
by default on standard build.

Jira NVGPU-4771

Change-Id: Idc5861fe71d9d510766cf242c6858e2faf97d7d0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547092
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2021-06-18 13:02:17 +00:00
committed by mobile promotions
parent ff75647d59
commit c7d43f5292
76 changed files with 182 additions and 200 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c
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@@ -54,7 +54,7 @@
#include <nvgpu/sec2/lsfm.h>
#endif
#if defined(CONFIG_NVGPU_NEXT)
#if defined(CONFIG_NVGPU_NON_FUSA)
#define PMU_PRIV_LOCKDOWN_RELEASE_POLLING_US (1U)
#endif
@@ -238,7 +238,7 @@ void nvgpu_pmu_rtos_cmdline_args_init(struct gk20a *g, struct nvgpu_pmu *pmu)
}
}
#if defined(CONFIG_NVGPU_NEXT)
#if defined(CONFIG_NVGPU_NON_FUSA)
void nvgpu_pmu_next_core_rtos_args_setup(struct gk20a *g,
struct nvgpu_pmu *pmu)
{
@@ -393,7 +393,7 @@ int nvgpu_pmu_rtos_init(struct gk20a *g)
g->ops.pmu.setup_apertures(g);
}
#if defined(CONFIG_NVGPU_NEXT)
#if defined(CONFIG_NVGPU_NON_FUSA)
if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
err = nvgpu_pmu_next_core_rtos_args_allocate(g, g->pmu);
if (err != 0) {
@@ -413,7 +413,7 @@ int nvgpu_pmu_rtos_init(struct gk20a *g)
nvgpu_pmu_enable_irq(g, true);
#if defined(CONFIG_NVGPU_NEXT)
#if defined(CONFIG_NVGPU_NON_FUSA)
if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
g->ops.falcon.bootstrap(g->pmu->flcn, 0U);
err = nvgpu_pmu_wait_for_priv_lockdown_release(g,
@@ -436,7 +436,7 @@ int nvgpu_pmu_rtos_init(struct gk20a *g)
if (err != 0) {
goto exit;
}
#if defined(CONFIG_NVGPU_NEXT)
#if defined(CONFIG_NVGPU_NON_FUSA)
if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
err = nvgpu_pmu_wait_for_priv_lockdown_release(g,
g->pmu->flcn, U32_MAX);