From c85d4c9e7fa2e2243d12905cfd73b6abe2be6122 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Wed, 12 Jun 2019 15:28:43 -0700 Subject: [PATCH] gpu: nvgpu: remove ZBC_STENCIL support for safety build Add CONFIG_NVGPU_GRAPHICS flag to enable the NVGPU_SUPPORT_ZBC_STENCIL support. Jira NVGPU-3580 Change-Id: I630430d5f2cca4a1230bdfe99e46346573030232 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/2135369 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_gv11b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_tu104.c | 2 ++ 5 files changed, 10 insertions(+) diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_gv11b.c index 375e2f045..91d142cab 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_gv11b.c @@ -40,7 +40,9 @@ void vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true); +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true); +#endif nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 052fb6bfd..785481067 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -1118,7 +1118,9 @@ int gm20b_init_hal(struct gk20a *g) #endif } +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, false); +#endif nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, false); nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 13f22b49a..ebfab192b 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -1199,7 +1199,9 @@ int gp10b_init_hal(struct gk20a *g) #endif } +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, false); +#endif nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true); nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index aa6b10c9a..5b8d986ca 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -1370,7 +1370,9 @@ int gv11b_init_hal(struct gk20a *g) #endif nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true); +#endif nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true); diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 42c82a3cc..0a158e84a 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1504,7 +1504,9 @@ int tu104_init_hal(struct gk20a *g) #endif nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_RTOS, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_RTOS_FBQ, true); +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, true); +#endif nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_VM, true);