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gpu: nvgpu: Add support for FECS errors

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Add retrieving error code for FECS errors.

Change-Id: I7d9dfc4723376272edb2e5b2ef06f71de1a06889
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/450351
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Tested-by: Chris Dragan <kdragan@nvidia.com>
This commit is contained in:
Terje Bergstrom
2014-08-01 16:15:54 +03:00
committed by Dan Willemsen
parent 0858498f7b
commit c8faa10d1d
2 changed files with 43 additions and 3 deletions
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30
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -4995,14 +4995,21 @@ static int gk20a_gr_handle_fecs_error(struct gk20a *g,
{
struct fifo_gk20a *f = &g->fifo;
struct channel_gk20a *ch = &f->channel[isr_data->chid];
u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_intr_r());
u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r());
gk20a_dbg_fn("");
gk20a_err(dev_from_gk20a(g),
"unhandled fecs error interrupt 0x%08x for channel %u",
gr_fecs_intr, ch->hw_chid);
gk20a_writel(g, gr_fecs_intr_r(), gr_fecs_intr);
if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) {
gk20a_err(dev_from_gk20a(g),
"firmware method error 0x%08x for offset 0x%04x",
gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)),
isr_data->data_lo);
}
gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr);
return -EINVAL;
}
@@ -5024,6 +5031,23 @@ static int gk20a_gr_handle_class_error(struct gk20a *g,
return -EINVAL;
}
static int gk20a_gr_handle_firmware_method(struct gk20a *g,
struct gr_isr_data *isr_data)
{
struct fifo_gk20a *f = &g->fifo;
struct channel_gk20a *ch = &f->channel[isr_data->chid];
gk20a_dbg_fn("");
gk20a_set_error_notifier(ch,
NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY);
gk20a_err(dev_from_gk20a(g),
"firmware method 0x%08x, offset 0x%08x for channel %u\n",
isr_data->class_num, isr_data->offset,
ch->hw_chid);
return -EINVAL;
}
static int gk20a_gr_handle_semaphore_pending(struct gk20a *g,
struct gr_isr_data *isr_data)
{
@@ -5513,7 +5537,7 @@ int gk20a_gr_isr(struct gk20a *g)
/* this one happens if someone tries to hit a non-whitelisted
* register using set_falcon[4] */
if (gr_intr & gr_intr_firmware_method_pending_f()) {
need_reset |= true;
need_reset |= gk20a_gr_handle_firmware_method(g, &isr_data);
gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "firmware method intr pending\n");
gk20a_writel(g, gr_intr_r(),
gr_intr_firmware_method_reset_f());

16
drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
View File

@@ -718,6 +718,22 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
{
return 0x21;
}
static inline u32 gr_fecs_host_int_status_r(void)
{
return 0x00409c18;
}
static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
{
return (v & 0x1) << 17;
}
static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
{
return (v & 0x1) << 18;
}
static inline u32 gr_fecs_host_int_clear_r(void)
{
return 0x00409c20;
}
static inline u32 gr_fecs_host_int_enable_r(void)
{
return 0x00409c24;