diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h
index c3e7800b8..c2a8368bb 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_CCSR_GV100_H
 #define NVGPU_HW_CCSR_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ccsr_channel_inst_r(u32 i)
 {
 	return 0x00800000U + i*8U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h
index 3779fd836..7e31730c7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_CE_GV100_H
 #define NVGPU_HW_CE_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ce_intr_status_r(u32 i)
 {
 	return 0x00104410U + i*128U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
index 82ed147bd..cc00de087 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_CTXSW_PROG_GV100_H
 #define NVGPU_HW_CTXSW_PROG_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ctxsw_prog_fecs_header_v(void)
 {
 	return 0x00000100U;
@@ -138,7 +140,7 @@ static inline u32 ctxsw_prog_main_image_pm_o(void)
 }
 static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
 {
@@ -150,7 +152,7 @@ static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void)
 }
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
 {
-	return 0x7U << 3U;
+	return U32(0x7U) << 3U;
 }
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
 {
@@ -394,7 +396,7 @@ static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
 {
@@ -422,7 +424,7 @@ static inline u32 ctxsw_prog_main_image_misc_options_o(void)
 }
 static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h
index 119a677cf..3997b1d49 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FALCON_GV100_H
 #define NVGPU_HW_FALCON_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 falcon_falcon_irqsset_r(void)
 {
 	return 0x00000000U;
@@ -310,7 +312,7 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
 }
 static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
 {
@@ -318,7 +320,7 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
 }
 static inline u32 falcon_falcon_cpuctl_stopped_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 {
@@ -326,7 +328,7 @@ static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 }
 static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
 {
@@ -390,11 +392,11 @@ static inline u32 falcon_falcon_dmactl_r(void)
 }
 static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
 {
@@ -494,7 +496,7 @@ static inline u32 falcon_falcon_exterrstat_r(void)
 }
 static inline u32 falcon_falcon_exterrstat_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
 {
@@ -518,7 +520,7 @@ static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
 }
 static inline u32 falcon_falcon_icd_cmd_opc_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
 {
@@ -550,7 +552,7 @@ static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
 }
 static inline u32 falcon_falcon_dmemc_offs_m(void)
 {
-	return 0x3fU << 2U;
+	return U32(0x3fU) << 2U;
 }
 static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
 {
@@ -558,7 +560,7 @@ static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
 }
 static inline u32 falcon_falcon_dmemc_blk_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
 {
@@ -586,7 +588,7 @@ static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
 }
 static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
index efe992ec4..9a9bcf397 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FB_GV100_H
 #define NVGPU_HW_FB_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 fb_fbhub_num_active_ltcs_r(void)
 {
 	return 0x00100800U;
@@ -66,7 +68,7 @@ static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_f(u32 v)
 }
 static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_m(void)
 {
-	return 0xffU << 16U;
+	return U32(0xffU) << 16U;
 }
 static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_v(u32 r)
 {
@@ -78,7 +80,7 @@ static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i)
 }
 static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_m(u32 i)
 {
-	return 0x1U << (16U + i*1U);
+	return U32(0x1U) << (16U + i*1U);
 }
 static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i)
 {
@@ -114,7 +116,7 @@ static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v)
 }
 static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void)
 {
-	return 0x1U << 25U;
+	return U32(0x1U) << 25U;
 }
 static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r)
 {
@@ -158,7 +160,7 @@ static inline u32 fb_mmu_ctrl_atomic_capability_mode_f(u32 v)
 }
 static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void)
 {
-	return 0x3U << 24U;
+	return U32(0x3U) << 24U;
 }
 static inline u32 fb_mmu_ctrl_atomic_capability_mode_v(u32 r)
 {
@@ -206,7 +208,7 @@ static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(u32 v)
 }
 static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(void)
 {
-	return 0x3U << 24U;
+	return U32(0x3U) << 24U;
 }
 static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(u32 r)
 {
@@ -254,7 +256,7 @@ static inline u32 fb_hshub_num_active_ltcs_use_nvlink_f(u32 v)
 }
 static inline u32 fb_hshub_num_active_ltcs_use_nvlink_m(void)
 {
-	return 0xffU << 16U;
+	return U32(0xffU) << 16U;
 }
 static inline u32 fb_hshub_num_active_ltcs_use_nvlink_v(u32 r)
 {
@@ -266,7 +268,7 @@ static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i)
 }
 static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_m(u32 i)
 {
-	return 0x1U << (16U + i*1U);
+	return U32(0x1U) << (16U + i*1U);
 }
 static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i)
 {
@@ -302,7 +304,7 @@ static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v)
 }
 static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void)
 {
-	return 0x1U << 25U;
+	return U32(0x1U) << 25U;
 }
 static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r)
 {
@@ -366,7 +368,7 @@ static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
 {
@@ -386,7 +388,7 @@ static inline u32 fb_mmu_invalidate_replay_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_replay_m(void)
 {
-	return 0x7U << 3U;
+	return U32(0x7U) << 3U;
 }
 static inline u32 fb_mmu_invalidate_replay_v(u32 r)
 {
@@ -418,7 +420,7 @@ static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_sys_membar_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
 {
@@ -438,7 +440,7 @@ static inline u32 fb_mmu_invalidate_ack_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_ack_m(void)
 {
-	return 0x3U << 7U;
+	return U32(0x3U) << 7U;
 }
 static inline u32 fb_mmu_invalidate_ack_v(u32 r)
 {
@@ -466,7 +468,7 @@ static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
 {
-	return 0x3fU << 9U;
+	return U32(0x3fU) << 9U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
 {
@@ -482,7 +484,7 @@ static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
 {
-	return 0x1fU << 15U;
+	return U32(0x1fU) << 15U;
 }
 static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
 {
@@ -498,7 +500,7 @@ static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
 {
@@ -522,7 +524,7 @@ static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
 {
-	return 0x7U << 24U;
+	return U32(0x7U) << 24U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
 {
@@ -570,7 +572,7 @@ static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_trigger_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
 {
@@ -594,7 +596,7 @@ static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
 }
 static inline u32 fb_mmu_debug_wr_aperture_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
 {
@@ -670,7 +672,7 @@ static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
 }
 static inline u32 fb_mmu_debug_ctrl_debug_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
 {
@@ -690,7 +692,7 @@ static inline u32 fb_niso_cfg1_sysmem_nvlink_f(u32 v)
 }
 static inline u32 fb_niso_cfg1_sysmem_nvlink_m(void)
 {
-	return 0x1U << 17U;
+	return U32(0x1U) << 17U;
 }
 static inline u32 fb_niso_cfg1_sysmem_nvlink_v(u32 r)
 {
@@ -714,7 +716,7 @@ static inline u32 fb_niso_intr_r(void)
 }
 static inline u32 fb_niso_intr_hub_access_counter_notify_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void)
 {
@@ -722,7 +724,7 @@ static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void)
 }
 static inline u32 fb_niso_intr_hub_access_counter_error_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void)
 {
@@ -730,7 +732,7 @@ static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void)
 }
 static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void)
 {
-	return 0x1U << 27U;
+	return U32(0x1U) << 27U;
 }
 static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void)
 {
@@ -738,7 +740,7 @@ static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void)
 }
 static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void)
 {
@@ -746,7 +748,7 @@ static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void)
 }
 static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void)
 {
-	return 0x1U << 29U;
+	return U32(0x1U) << 29U;
 }
 static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void)
 {
@@ -754,7 +756,7 @@ static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void)
 }
 static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void)
 {
@@ -762,7 +764,7 @@ static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void)
 }
 static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void)
 {
@@ -842,7 +844,7 @@ static inline u32 fb_niso_intr_en_set__size_1_v(void)
 }
 static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void)
 {
@@ -850,7 +852,7 @@ static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void)
 }
 static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void)
 {
@@ -858,7 +860,7 @@ static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void)
 }
 static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void)
 {
-	return 0x1U << 27U;
+	return U32(0x1U) << 27U;
 }
 static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void)
 {
@@ -866,7 +868,7 @@ static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void)
 }
 static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void)
 {
@@ -874,7 +876,7 @@ static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void)
 }
 static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void)
 {
-	return 0x1U << 29U;
+	return U32(0x1U) << 29U;
 }
 static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void)
 {
@@ -882,7 +884,7 @@ static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void)
 }
 static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void)
 {
@@ -890,7 +892,7 @@ static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(voi
 }
 static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void)
 {
@@ -906,7 +908,7 @@ static inline u32 fb_niso_intr_en_clr__size_1_v(void)
 }
 static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void)
 {
@@ -914,7 +916,7 @@ static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void)
 }
 static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void)
 {
@@ -922,7 +924,7 @@ static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void)
 }
 static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void)
 {
-	return 0x1U << 27U;
+	return U32(0x1U) << 27U;
 }
 static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void)
 {
@@ -930,7 +932,7 @@ static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void)
 }
 static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void)
 {
@@ -938,7 +940,7 @@ static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void)
 }
 static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void)
 {
-	return 0x1U << 29U;
+	return U32(0x1U) << 29U;
 }
 static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void)
 {
@@ -946,7 +948,7 @@ static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void)
 }
 static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void)
 {
@@ -954,7 +956,7 @@ static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(voi
 }
 static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void)
 {
@@ -1070,7 +1072,7 @@ static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v)
 }
 static inline u32 fb_mmu_fault_buffer_get_ptr_m(void)
 {
-	return 0xfffffU << 0U;
+	return U32(0xfffffU) << 0U;
 }
 static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r)
 {
@@ -1082,7 +1084,7 @@ static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v)
 }
 static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void)
 {
@@ -1098,7 +1100,7 @@ static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v)
 }
 static inline u32 fb_mmu_fault_buffer_get_overflow_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void)
 {
@@ -1218,7 +1220,7 @@ static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v)
 }
 static inline u32 fb_mmu_fault_buffer_size_enable_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r)
 {
@@ -1362,7 +1364,7 @@ static inline u32 fb_mmu_fault_status_r(void)
 }
 static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void)
 {
@@ -1382,7 +1384,7 @@ static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void)
 }
 static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void)
 {
@@ -1402,7 +1404,7 @@ static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void)
 }
 static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void)
 {
@@ -1422,7 +1424,7 @@ static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void)
 }
 static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void)
 {
@@ -1442,7 +1444,7 @@ static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void)
 }
 static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void)
 {
@@ -1462,7 +1464,7 @@ static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void)
 }
 static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void)
 {
@@ -1482,7 +1484,7 @@ static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void)
 }
 static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void)
 {
@@ -1502,7 +1504,7 @@ static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void)
 }
 static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void)
 {
@@ -1522,7 +1524,7 @@ static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void)
 }
 static inline u32 fb_mmu_fault_status_replayable_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 fb_mmu_fault_status_replayable_set_v(void)
 {
@@ -1538,7 +1540,7 @@ static inline u32 fb_mmu_fault_status_replayable_reset_f(void)
 }
 static inline u32 fb_mmu_fault_status_non_replayable_m(void)
 {
-	return 0x1U << 9U;
+	return U32(0x1U) << 9U;
 }
 static inline u32 fb_mmu_fault_status_non_replayable_set_v(void)
 {
@@ -1554,7 +1556,7 @@ static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void)
 }
 static inline u32 fb_mmu_fault_status_replayable_error_m(void)
 {
-	return 0x1U << 10U;
+	return U32(0x1U) << 10U;
 }
 static inline u32 fb_mmu_fault_status_replayable_error_set_v(void)
 {
@@ -1570,7 +1572,7 @@ static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void)
 }
 static inline u32 fb_mmu_fault_status_non_replayable_error_m(void)
 {
-	return 0x1U << 11U;
+	return U32(0x1U) << 11U;
 }
 static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void)
 {
@@ -1586,7 +1588,7 @@ static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void)
 }
 static inline u32 fb_mmu_fault_status_replayable_overflow_m(void)
 {
-	return 0x1U << 12U;
+	return U32(0x1U) << 12U;
 }
 static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void)
 {
@@ -1602,7 +1604,7 @@ static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void)
 }
 static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void)
 {
-	return 0x1U << 13U;
+	return U32(0x1U) << 13U;
 }
 static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void)
 {
@@ -1618,7 +1620,7 @@ static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void)
 }
 static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void)
 {
-	return 0x1U << 14U;
+	return U32(0x1U) << 14U;
 }
 static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void)
 {
@@ -1630,7 +1632,7 @@ static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void)
 }
 static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void)
 {
-	return 0x1U << 15U;
+	return U32(0x1U) << 15U;
 }
 static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void)
 {
@@ -1642,7 +1644,7 @@ static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void
 }
 static inline u32 fb_mmu_fault_status_busy_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 fb_mmu_fault_status_busy_true_v(void)
 {
@@ -1654,7 +1656,7 @@ static inline u32 fb_mmu_fault_status_busy_true_f(void)
 }
 static inline u32 fb_mmu_fault_status_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 fb_mmu_fault_status_valid_set_v(void)
 {
@@ -1706,7 +1708,7 @@ static inline u32 fb_mmu_priv_level_mask_write_violation_f(u32 v)
 }
 static inline u32 fb_mmu_priv_level_mask_write_violation_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 fb_mmu_priv_level_mask_write_violation_v(u32 r)
 {
@@ -1722,7 +1724,7 @@ static inline u32 fb_hshub_config0_sysmem_nvlink_mask_f(u32 v)
 }
 static inline u32 fb_hshub_config0_sysmem_nvlink_mask_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 fb_hshub_config0_sysmem_nvlink_mask_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h
index f44495a16..7db73183b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FIFO_GV100_H
 #define NVGPU_HW_FIFO_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 fifo_userd_writeback_r(void)
 {
 	return 0x0000225cU;
@@ -226,7 +228,7 @@ static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
 }
 static inline u32 fifo_intr_en_0_sched_error_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 fifo_intr_en_1_r(void)
 {
@@ -274,7 +276,7 @@ static inline u32 fifo_fb_timeout_r(void)
 }
 static inline u32 fifo_fb_timeout_period_m(void)
 {
-	return 0x3fffffffU << 0U;
+	return U32(0x3fffffffU) << 0U;
 }
 static inline u32 fifo_fb_timeout_period_max_f(void)
 {
@@ -294,7 +296,7 @@ static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
 }
 static inline u32 fifo_sched_disable_runlist_m(u32 i)
 {
-	return 0x1U << (0U + i*1U);
+	return U32(0x1U) << (0U + i*1U);
 }
 static inline u32 fifo_sched_disable_true_v(void)
 {
@@ -310,7 +312,7 @@ static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i)
 }
 static inline u32 fifo_runlist_preempt_runlist_m(u32 i)
 {
-	return 0x1U << (0U + i*1U);
+	return U32(0x1U) << (0U + i*1U);
 }
 static inline u32 fifo_runlist_preempt_runlist_pending_v(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h
index 46d29d791..b2a8ddea1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FLUSH_GV100_H
 #define NVGPU_HW_FLUSH_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 flush_l2_system_invalidate_r(void)
 {
 	return 0x00070004U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h
index a2c46b3df..f833ce9c9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FUSE_GV100_H
 #define NVGPU_HW_FUSE_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 fuse_status_opt_gpc_r(void)
 {
 	return 0x00021c1cU;
@@ -78,7 +80,7 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
 {
@@ -94,7 +96,7 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
 {
@@ -118,7 +120,7 @@ static inline u32 fuse_status_opt_fbio_data_f(u32 v)
 }
 static inline u32 fuse_status_opt_fbio_data_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 fuse_status_opt_fbio_data_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h
index 241d7df47..e87196357 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_GMMU_GV100_H
 #define NVGPU_HW_GMMU_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 gmmu_new_pde_is_pte_w(void)
 {
 	return 0U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
index 7652661e9..38bf7950f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_GR_GV100_H
 #define NVGPU_HW_GR_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 gr_intr_r(void)
 {
 	return 0x00400100U;
@@ -166,39 +168,39 @@ static inline u32 gr_exception_r(void)
 }
 static inline u32 gr_exception_fe_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_exception_gpc_m(void)
 {
-	return 0x1U << 24U;
+	return U32(0x1U) << 24U;
 }
 static inline u32 gr_exception_memfmt_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_exception_ds_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_exception_sked_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 gr_exception_pd_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_exception_scc_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 gr_exception_ssync_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 gr_exception_mme_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 gr_exception1_r(void)
 {
@@ -218,7 +220,7 @@ static inline u32 gr_exception_en_r(void)
 }
 static inline u32 gr_exception_en_fe_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_exception_en_fe_enabled_f(void)
 {
@@ -226,7 +228,7 @@ static inline u32 gr_exception_en_fe_enabled_f(void)
 }
 static inline u32 gr_exception_en_gpc_m(void)
 {
-	return 0x1U << 24U;
+	return U32(0x1U) << 24U;
 }
 static inline u32 gr_exception_en_gpc_enabled_f(void)
 {
@@ -234,7 +236,7 @@ static inline u32 gr_exception_en_gpc_enabled_f(void)
 }
 static inline u32 gr_exception_en_memfmt_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_exception_en_memfmt_enabled_f(void)
 {
@@ -242,7 +244,7 @@ static inline u32 gr_exception_en_memfmt_enabled_f(void)
 }
 static inline u32 gr_exception_en_ds_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_exception_en_ds_enabled_f(void)
 {
@@ -250,7 +252,7 @@ static inline u32 gr_exception_en_ds_enabled_f(void)
 }
 static inline u32 gr_exception_en_pd_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_exception_en_pd_enabled_f(void)
 {
@@ -258,7 +260,7 @@ static inline u32 gr_exception_en_pd_enabled_f(void)
 }
 static inline u32 gr_exception_en_scc_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 gr_exception_en_scc_enabled_f(void)
 {
@@ -266,7 +268,7 @@ static inline u32 gr_exception_en_scc_enabled_f(void)
 }
 static inline u32 gr_exception_en_ssync_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 gr_exception_en_ssync_enabled_f(void)
 {
@@ -274,7 +276,7 @@ static inline u32 gr_exception_en_ssync_enabled_f(void)
 }
 static inline u32 gr_exception_en_mme_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 gr_exception_en_mme_enabled_f(void)
 {
@@ -282,7 +284,7 @@ static inline u32 gr_exception_en_mme_enabled_f(void)
 }
 static inline u32 gr_exception_en_sked_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 gr_exception_en_sked_enabled_f(void)
 {
@@ -462,7 +464,7 @@ static inline u32 gr_activity_4_gpc0_f(u32 v)
 }
 static inline u32 gr_activity_4_gpc0_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 gr_activity_4_gpc0_v(u32 r)
 {
@@ -486,7 +488,7 @@ static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
 }
 static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
 {
@@ -498,7 +500,7 @@ static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
 }
 static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_pri_sked_activity_r(void)
 {
@@ -602,67 +604,67 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void)
 {
-	return 0x1U << 9U;
+	return U32(0x1U) << 9U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void)
 {
-	return 0x1U << 10U;
+	return U32(0x1U) << 10U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void)
 {
-	return 0x1U << 11U;
+	return U32(0x1U) << 11U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void)
 {
-	return 0x1U << 12U;
+	return U32(0x1U) << 12U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void)
 {
-	return 0x1U << 13U;
+	return U32(0x1U) << 13U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void)
 {
-	return 0x1U << 14U;
+	return U32(0x1U) << 14U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void)
 {
-	return 0x1U << 15U;
+	return U32(0x1U) << 15U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
 {
@@ -706,19 +708,19 @@ static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
 {
@@ -762,35 +764,35 @@ static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
 {
@@ -970,7 +972,7 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void)
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void)
 {
@@ -978,7 +980,7 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void)
 {
@@ -986,7 +988,7 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void)
 {
@@ -994,7 +996,7 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void)
 {
@@ -1002,7 +1004,7 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void)
 {
@@ -1102,11 +1104,11 @@ static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
 }
 static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_fecs_os_r(void)
 {
@@ -1174,7 +1176,7 @@ static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
 }
 static inline u32 gr_fecs_icd_cmd_opc_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
 {
@@ -1238,7 +1240,7 @@ static inline u32 gr_fecs_dmemc_offs_f(u32 v)
 }
 static inline u32 gr_fecs_dmemc_offs_m(void)
 {
-	return 0x3fU << 2U;
+	return U32(0x3fU) << 2U;
 }
 static inline u32 gr_fecs_dmemc_offs_v(u32 r)
 {
@@ -1330,7 +1332,7 @@ static inline u32 gr_fecs_current_ctx_target_f(u32 v)
 }
 static inline u32 gr_fecs_current_ctx_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_fecs_current_ctx_target_v(u32 r)
 {
@@ -1358,7 +1360,7 @@ static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
 }
 static inline u32 gr_fecs_current_ctx_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
 {
@@ -1554,7 +1556,7 @@ static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
 {
-	return 0x1U << 10U;
+	return U32(0x1U) << 10U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
 {
@@ -1622,7 +1624,7 @@ static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
 }
 static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
 {
-	return 0x1fU << 0U;
+	return U32(0x1fU) << 0U;
 }
 static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
 {
@@ -1638,7 +1640,7 @@ static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
 }
 static inline u32 gr_fecs_fs_num_available_fbps_m(void)
 {
-	return 0x1fU << 16U;
+	return U32(0x1fU) << 16U;
 }
 static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
 {
@@ -1666,7 +1668,7 @@ static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
 }
 static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
 {
@@ -1686,7 +1688,7 @@ static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
 }
 static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
 {
-	return 0x1U << 12U;
+	return U32(0x1U) << 12U;
 }
 static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
 {
@@ -1710,7 +1712,7 @@ static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
 }
 static inline u32 gr_fecs_new_ctx_ptr_m(void)
 {
-	return 0xfffffffU << 0U;
+	return U32(0xfffffffU) << 0U;
 }
 static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
 {
@@ -1726,7 +1728,7 @@ static inline u32 gr_fecs_new_ctx_target_f(u32 v)
 }
 static inline u32 gr_fecs_new_ctx_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_fecs_new_ctx_target_v(u32 r)
 {
@@ -1742,7 +1744,7 @@ static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
 }
 static inline u32 gr_fecs_new_ctx_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
 {
@@ -1762,7 +1764,7 @@ static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
 }
 static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
 {
-	return 0xfffffffU << 0U;
+	return U32(0xfffffffU) << 0U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
 {
@@ -1778,7 +1780,7 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
 {
@@ -1798,7 +1800,7 @@ static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
 }
 static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
 {
-	return 0x1fU << 0U;
+	return U32(0x1fU) << 0U;
 }
 static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
 {
@@ -2074,7 +2076,7 @@ static inline u32 gr_ds_zbc_z_val_f(u32 v)
 }
 static inline u32 gr_ds_zbc_z_val_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 gr_ds_zbc_z_val_v(u32 r)
 {
@@ -2162,7 +2164,7 @@ static inline u32 gr_ds_hww_esr_reset_f(u32 v)
 }
 static inline u32 gr_ds_hww_esr_reset_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_ds_hww_esr_reset_v(u32 r)
 {
@@ -2194,7 +2196,7 @@ static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
 }
 static inline u32 gr_ds_hww_esr_2_reset_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
 {
@@ -2406,7 +2408,7 @@ static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
 {
-	return 0x3ffU << 10U;
+	return U32(0x3ffU) << 10U;
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
 {
@@ -2462,7 +2464,7 @@ static inline u32 gr_sked_hww_esr_en_r(void)
 }
 static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void)
 {
-	return 0x1U << 25U;
+	return U32(0x1U) << 25U;
 }
 static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void)
 {
@@ -2558,7 +2560,7 @@ static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
 }
 static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
 {
@@ -2578,7 +2580,7 @@ static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
 }
 static inline u32 gr_gpccs_rc_lane_size_v_m(void)
 {
-	return 0xffffffU << 0U;
+	return U32(0xffffffU) << 0U;
 }
 static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
 {
@@ -2706,7 +2708,7 @@ static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
 }
 static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
 {
@@ -2722,7 +2724,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
 {
-	return 0x3fffffU << 0U;
+	return U32(0x3fffffU) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
 {
@@ -2750,7 +2752,7 @@ static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
 {
@@ -2798,7 +2800,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
 {
-	return 0x1fffffU << 0U;
+	return U32(0x1fffffU) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
 {
@@ -2818,7 +2820,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
 {
@@ -2842,7 +2844,7 @@ static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
 {
@@ -2866,7 +2868,7 @@ static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
 }
 static inline u32 gr_gpccs_falcon_addr_msb_m(void)
 {
-	return 0x3fU << 6U;
+	return U32(0x3fU) << 6U;
 }
 static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
 {
@@ -2890,7 +2892,7 @@ static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
 }
 static inline u32 gr_gpccs_falcon_addr_ext_m(void)
 {
-	return 0xfffU << 0U;
+	return U32(0xfffU) << 0U;
 }
 static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
 {
@@ -2914,11 +2916,11 @@ static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
 }
 static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpccs_imemc_r(u32 i)
 {
@@ -2994,7 +2996,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
 {
@@ -3022,7 +3024,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
 {
-	return 0x7ffU << 0U;
+	return U32(0x7ffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
 {
@@ -3046,7 +3048,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
 {
@@ -3126,7 +3128,7 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
 {
-	return 0x3fffffU << 0U;
+	return U32(0x3fffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
 {
@@ -3506,7 +3508,7 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
 }
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void)
 {
@@ -3518,7 +3520,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void)
 }
 static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r)
 {
@@ -3542,7 +3544,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void)
 {
@@ -3554,7 +3556,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void)
 {
@@ -3710,11 +3712,11 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void)
 {
-	return 0xffU << 16U;
+	return U32(0xffU) << 16U;
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void)
 {
-	return 0xfU << 24U;
+	return U32(0xfU) << 24U;
 }
 static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void)
 {
@@ -3750,7 +3752,7 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
 {
@@ -3766,7 +3768,7 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
 {
@@ -3854,11 +3856,11 @@ static inline u32 gr_bes_crop_debug3_r(void)
 }
 static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void)
 {
@@ -3870,7 +3872,7 @@ static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void)
 }
 static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void)
 {
@@ -3886,7 +3888,7 @@ static inline u32 gr_bes_crop_debug4_r(void)
 }
 static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void)
 {
-	return 0x1U << 18U;
+	return U32(0x1U) << 18U;
 }
 static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void)
 {
@@ -3930,7 +3932,7 @@ static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void)
 {
-	return 0x1U << 19U;
+	return U32(0x1U) << 19U;
 }
 static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void)
 {
@@ -3942,7 +3944,7 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v)
 {
@@ -3950,11 +3952,11 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void)
 {
-	return 0x1U << 10U;
+	return U32(0x1U) << 10U;
 }
 static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void)
 {
@@ -3994,39 +3996,39 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
 {
-	return 0x1U << 11U;
+	return U32(0x1U) << 11U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
 {
-	return 0x3U << 3U;
+	return U32(0x3U) << 3U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
 {
-	return 0x3U << 5U;
+	return U32(0x3U) << 5U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
 {
@@ -4086,7 +4088,7 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
 {
-	return 0x7U << 8U;
+	return U32(0x7U) << 8U;
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
 {
@@ -4098,7 +4100,7 @@ static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
 {
-	return 0x3U << 11U;
+	return U32(0x3U) << 11U;
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
 {
@@ -4114,6 +4116,6 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
 }
 static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
 {
-	return 0x1ffU << 0U;
+	return U32(0x1ffU) << 0U;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
index c774dda0d..7133837e0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_IOCTRL_GV100_H
 #define NVGPU_HW_IOCTRL_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ioctrl_reset_r(void)
 {
 	return 0x00000140U;
@@ -70,7 +72,7 @@ static inline u32 ioctrl_reset_linkreset_f(u32 v)
 }
 static inline u32 ioctrl_reset_linkreset_m(void)
 {
-	return 0x3fU << 8U;
+	return U32(0x3fU) << 8U;
 }
 static inline u32 ioctrl_reset_linkreset_v(u32 r)
 {
@@ -86,7 +88,7 @@ static inline u32 ioctrl_debug_reset_link_f(u32 v)
 }
 static inline u32 ioctrl_debug_reset_link_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 ioctrl_debug_reset_link_v(u32 r)
 {
@@ -98,7 +100,7 @@ static inline u32 ioctrl_debug_reset_common_f(u32 v)
 }
 static inline u32 ioctrl_debug_reset_common_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 ioctrl_debug_reset_common_v(u32 r)
 {
@@ -118,7 +120,7 @@ static inline u32 ioctrl_clock_control_clkdis_f(u32 v)
 }
 static inline u32 ioctrl_clock_control_clkdis_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 ioctrl_clock_control_clkdis_v(u32 r)
 {
@@ -134,7 +136,7 @@ static inline u32 ioctrl_top_intr_0_status_link_f(u32 v)
 }
 static inline u32 ioctrl_top_intr_0_status_link_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 ioctrl_top_intr_0_status_link_v(u32 r)
 {
@@ -146,7 +148,7 @@ static inline u32 ioctrl_top_intr_0_status_common_f(u32 v)
 }
 static inline u32 ioctrl_top_intr_0_status_common_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 ioctrl_top_intr_0_status_common_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h
index 05fd2ff53..cde2c4d98 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_IOCTRLMIF_GV100_H
 #define NVGPU_HW_IOCTRLMIF_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ioctrlmif_rx_err_contain_en_0_r(void)
 {
 	return 0x00000e0cU;
@@ -66,7 +68,7 @@ static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(u32 r)
 {
@@ -86,7 +88,7 @@ static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(u32 r)
 {
@@ -110,7 +112,7 @@ static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(u32 r)
 {
@@ -122,7 +124,7 @@ static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(u32 r)
 {
@@ -138,7 +140,7 @@ static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(u32 r)
 {
@@ -150,7 +152,7 @@ static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(u32 r)
 {
@@ -166,7 +168,7 @@ static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_v(u32 r)
 {
@@ -178,7 +180,7 @@ static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(u32 r)
 {
@@ -198,7 +200,7 @@ static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(u32 r)
 {
@@ -218,7 +220,7 @@ static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(u32 r)
 {
@@ -242,7 +244,7 @@ static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(u32 r)
 {
@@ -254,7 +256,7 @@ static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(u32 r)
 {
@@ -270,7 +272,7 @@ static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(u32 r)
 {
@@ -282,7 +284,7 @@ static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(u32 r)
 {
@@ -298,7 +300,7 @@ static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_v(u32 r)
 {
@@ -310,7 +312,7 @@ static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_f(u32 v)
 }
 static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h
index a389388d8..bdd4688f0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_LTC_GV100_H
 #define NVGPU_HW_LTC_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ltc_pltcg_base_v(void)
 {
 	return 0x00140000U;
@@ -90,7 +92,7 @@ static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
 }
 static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
 {
-	return 0x1U << 15U;
+	return U32(0x1U) << 15U;
 }
 static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
 {
@@ -266,7 +268,7 @@ static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
 {
@@ -286,7 +288,7 @@ static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v)
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r)
 {
@@ -362,11 +364,11 @@ static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
 }
 static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void)
 {
-	return 0x1U << 21U;
+	return U32(0x1U) << 21U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f(void)
 {
@@ -378,7 +380,7 @@ static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f(void)
 }
 static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
 {
@@ -398,7 +400,7 @@ static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
 {
@@ -406,7 +408,7 @@ static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
 {
-	return 0xffU << 16U;
+	return U32(0xffU) << 16U;
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
index 913dc6e75..9dc11bdcb 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_MC_GV100_H
 #define NVGPU_HW_MC_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 mc_boot_0_r(void)
 {
 	return 0x00000000U;
@@ -146,7 +148,7 @@ static inline u32 mc_enable_pmedia_f(u32 v)
 }
 static inline u32 mc_enable_pmedia_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 mc_enable_pmedia_v(u32 r)
 {
@@ -154,7 +156,7 @@ static inline u32 mc_enable_pmedia_v(u32 r)
 }
 static inline u32 mc_enable_ce0_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 mc_enable_pfifo_enabled_f(void)
 {
@@ -182,7 +184,7 @@ static inline u32 mc_enable_pfb_enabled_f(void)
 }
 static inline u32 mc_enable_ce2_m(void)
 {
-	return 0x1U << 21U;
+	return U32(0x1U) << 21U;
 }
 static inline u32 mc_enable_ce2_enabled_f(void)
 {
@@ -242,7 +244,7 @@ static inline u32 mc_enable_pb_0_f(u32 v)
 }
 static inline u32 mc_enable_pb_0_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 mc_enable_pb_0_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
index e2ee4adbb..c0db8613e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_MINION_GV100_H
 #define NVGPU_HW_MINION_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 minion_minion_status_r(void)
 {
 	return 0x00000830U;
@@ -66,7 +68,7 @@ static inline u32 minion_minion_status_status_f(u32 v)
 }
 static inline u32 minion_minion_status_status_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 minion_minion_status_status_v(u32 r)
 {
@@ -86,7 +88,7 @@ static inline u32 minion_minion_status_intr_code_f(u32 v)
 }
 static inline u32 minion_minion_status_intr_code_m(void)
 {
-	return 0xffffffU << 8U;
+	return U32(0xffffffU) << 8U;
 }
 static inline u32 minion_minion_status_intr_code_v(u32 r)
 {
@@ -142,7 +144,7 @@ static inline u32 minion_falcon_irqmset_wdtmr_f(u32 v)
 }
 static inline u32 minion_falcon_irqmset_wdtmr_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 minion_falcon_irqmset_wdtmr_v(u32 r)
 {
@@ -162,7 +164,7 @@ static inline u32 minion_falcon_irqmset_halt_f(u32 v)
 }
 static inline u32 minion_falcon_irqmset_halt_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 minion_falcon_irqmset_halt_v(u32 r)
 {
@@ -182,7 +184,7 @@ static inline u32 minion_falcon_irqmset_exterr_f(u32 v)
 }
 static inline u32 minion_falcon_irqmset_exterr_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 minion_falcon_irqmset_exterr_v(u32 r)
 {
@@ -202,7 +204,7 @@ static inline u32 minion_falcon_irqmset_swgen0_f(u32 v)
 }
 static inline u32 minion_falcon_irqmset_swgen0_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 minion_falcon_irqmset_swgen0_v(u32 r)
 {
@@ -222,7 +224,7 @@ static inline u32 minion_falcon_irqmset_swgen1_f(u32 v)
 }
 static inline u32 minion_falcon_irqmset_swgen1_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 minion_falcon_irqmset_swgen1_v(u32 r)
 {
@@ -246,7 +248,7 @@ static inline u32 minion_falcon_irqdest_host_wdtmr_f(u32 v)
 }
 static inline u32 minion_falcon_irqdest_host_wdtmr_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 minion_falcon_irqdest_host_wdtmr_v(u32 r)
 {
@@ -266,7 +268,7 @@ static inline u32 minion_falcon_irqdest_host_halt_f(u32 v)
 }
 static inline u32 minion_falcon_irqdest_host_halt_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 minion_falcon_irqdest_host_halt_v(u32 r)
 {
@@ -286,7 +288,7 @@ static inline u32 minion_falcon_irqdest_host_exterr_f(u32 v)
 }
 static inline u32 minion_falcon_irqdest_host_exterr_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 minion_falcon_irqdest_host_exterr_v(u32 r)
 {
@@ -306,7 +308,7 @@ static inline u32 minion_falcon_irqdest_host_swgen0_f(u32 v)
 }
 static inline u32 minion_falcon_irqdest_host_swgen0_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 minion_falcon_irqdest_host_swgen0_v(u32 r)
 {
@@ -326,7 +328,7 @@ static inline u32 minion_falcon_irqdest_host_swgen1_f(u32 v)
 }
 static inline u32 minion_falcon_irqdest_host_swgen1_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 minion_falcon_irqdest_host_swgen1_v(u32 r)
 {
@@ -346,7 +348,7 @@ static inline u32 minion_falcon_irqdest_target_wdtmr_f(u32 v)
 }
 static inline u32 minion_falcon_irqdest_target_wdtmr_m(void)
 {
-	return 0x1U << 17U;
+	return U32(0x1U) << 17U;
 }
 static inline u32 minion_falcon_irqdest_target_wdtmr_v(u32 r)
 {
@@ -366,7 +368,7 @@ static inline u32 minion_falcon_irqdest_target_halt_f(u32 v)
 }
 static inline u32 minion_falcon_irqdest_target_halt_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 minion_falcon_irqdest_target_halt_v(u32 r)
 {
@@ -386,7 +388,7 @@ static inline u32 minion_falcon_irqdest_target_exterr_f(u32 v)
 }
 static inline u32 minion_falcon_irqdest_target_exterr_m(void)
 {
-	return 0x1U << 21U;
+	return U32(0x1U) << 21U;
 }
 static inline u32 minion_falcon_irqdest_target_exterr_v(u32 r)
 {
@@ -406,7 +408,7 @@ static inline u32 minion_falcon_irqdest_target_swgen0_f(u32 v)
 }
 static inline u32 minion_falcon_irqdest_target_swgen0_m(void)
 {
-	return 0x1U << 22U;
+	return U32(0x1U) << 22U;
 }
 static inline u32 minion_falcon_irqdest_target_swgen0_v(u32 r)
 {
@@ -426,7 +428,7 @@ static inline u32 minion_falcon_irqdest_target_swgen1_f(u32 v)
 }
 static inline u32 minion_falcon_irqdest_target_swgen1_m(void)
 {
-	return 0x1U << 23U;
+	return U32(0x1U) << 23U;
 }
 static inline u32 minion_falcon_irqdest_target_swgen1_v(u32 r)
 {
@@ -458,7 +460,7 @@ static inline u32 minion_minion_intr_fatal_f(u32 v)
 }
 static inline u32 minion_minion_intr_fatal_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 minion_minion_intr_fatal_v(u32 r)
 {
@@ -470,7 +472,7 @@ static inline u32 minion_minion_intr_nonfatal_f(u32 v)
 }
 static inline u32 minion_minion_intr_nonfatal_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 minion_minion_intr_nonfatal_v(u32 r)
 {
@@ -482,7 +484,7 @@ static inline u32 minion_minion_intr_falcon_stall_f(u32 v)
 }
 static inline u32 minion_minion_intr_falcon_stall_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 minion_minion_intr_falcon_stall_v(u32 r)
 {
@@ -494,7 +496,7 @@ static inline u32 minion_minion_intr_falcon_nostall_f(u32 v)
 }
 static inline u32 minion_minion_intr_falcon_nostall_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 minion_minion_intr_falcon_nostall_v(u32 r)
 {
@@ -506,7 +508,7 @@ static inline u32 minion_minion_intr_link_f(u32 v)
 }
 static inline u32 minion_minion_intr_link_m(void)
 {
-	return 0xffffU << 16U;
+	return U32(0xffffU) << 16U;
 }
 static inline u32 minion_minion_intr_link_v(u32 r)
 {
@@ -526,7 +528,7 @@ static inline u32 minion_minion_intr_stall_en_fatal_f(u32 v)
 }
 static inline u32 minion_minion_intr_stall_en_fatal_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 minion_minion_intr_stall_en_fatal_v(u32 r)
 {
@@ -554,7 +556,7 @@ static inline u32 minion_minion_intr_stall_en_nonfatal_f(u32 v)
 }
 static inline u32 minion_minion_intr_stall_en_nonfatal_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 minion_minion_intr_stall_en_nonfatal_v(u32 r)
 {
@@ -582,7 +584,7 @@ static inline u32 minion_minion_intr_stall_en_falcon_stall_f(u32 v)
 }
 static inline u32 minion_minion_intr_stall_en_falcon_stall_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 minion_minion_intr_stall_en_falcon_stall_v(u32 r)
 {
@@ -610,7 +612,7 @@ static inline u32 minion_minion_intr_stall_en_falcon_nostall_f(u32 v)
 }
 static inline u32 minion_minion_intr_stall_en_falcon_nostall_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 minion_minion_intr_stall_en_falcon_nostall_v(u32 r)
 {
@@ -638,7 +640,7 @@ static inline u32 minion_minion_intr_stall_en_link_f(u32 v)
 }
 static inline u32 minion_minion_intr_stall_en_link_m(void)
 {
-	return 0xffffU << 16U;
+	return U32(0xffffU) << 16U;
 }
 static inline u32 minion_minion_intr_stall_en_link_v(u32 r)
 {
@@ -878,7 +880,7 @@ static inline u32 minion_nvlink_link_intr_code_f(u32 v)
 }
 static inline u32 minion_nvlink_link_intr_code_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 minion_nvlink_link_intr_code_v(u32 r)
 {
@@ -922,7 +924,7 @@ static inline u32 minion_nvlink_link_intr_subcode_f(u32 v)
 }
 static inline u32 minion_nvlink_link_intr_subcode_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 minion_nvlink_link_intr_subcode_v(u32 r)
 {
@@ -934,7 +936,7 @@ static inline u32 minion_nvlink_link_intr_state_f(u32 v)
 }
 static inline u32 minion_nvlink_link_intr_state_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 minion_nvlink_link_intr_state_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h
index 52e92b8a0..bb9f8f269 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_NVL_GV100_H
 #define NVGPU_HW_NVL_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 nvl_link_state_r(void)
 {
 	return 0x00000000U;
@@ -66,7 +68,7 @@ static inline u32 nvl_link_state_state_f(u32 v)
 }
 static inline u32 nvl_link_state_state_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 nvl_link_state_state_v(u32 r)
 {
@@ -142,7 +144,7 @@ static inline u32 nvl_link_state_an0_busy_f(u32 v)
 }
 static inline u32 nvl_link_state_an0_busy_m(void)
 {
-	return 0x1U << 12U;
+	return U32(0x1U) << 12U;
 }
 static inline u32 nvl_link_state_an0_busy_v(u32 r)
 {
@@ -154,7 +156,7 @@ static inline u32 nvl_link_state_tl_busy_f(u32 v)
 }
 static inline u32 nvl_link_state_tl_busy_m(void)
 {
-	return 0x1U << 13U;
+	return U32(0x1U) << 13U;
 }
 static inline u32 nvl_link_state_tl_busy_v(u32 r)
 {
@@ -166,7 +168,7 @@ static inline u32 nvl_link_state_dbg_substate_f(u32 v)
 }
 static inline u32 nvl_link_state_dbg_substate_m(void)
 {
-	return 0xffffU << 16U;
+	return U32(0xffffU) << 16U;
 }
 static inline u32 nvl_link_state_dbg_substate_v(u32 r)
 {
@@ -182,7 +184,7 @@ static inline u32 nvl_link_activity_blkact_f(u32 v)
 }
 static inline u32 nvl_link_activity_blkact_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 nvl_link_activity_blkact_v(u32 r)
 {
@@ -198,7 +200,7 @@ static inline u32 nvl_sublink_activity_blkact0_f(u32 v)
 }
 static inline u32 nvl_sublink_activity_blkact0_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 nvl_sublink_activity_blkact0_v(u32 r)
 {
@@ -210,7 +212,7 @@ static inline u32 nvl_sublink_activity_blkact1_f(u32 v)
 }
 static inline u32 nvl_sublink_activity_blkact1_m(void)
 {
-	return 0x7U << 8U;
+	return U32(0x7U) << 8U;
 }
 static inline u32 nvl_sublink_activity_blkact1_v(u32 r)
 {
@@ -226,7 +228,7 @@ static inline u32 nvl_link_config_ac_safe_en_f(u32 v)
 }
 static inline u32 nvl_link_config_ac_safe_en_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 nvl_link_config_ac_safe_en_v(u32 r)
 {
@@ -246,7 +248,7 @@ static inline u32 nvl_link_config_link_en_f(u32 v)
 }
 static inline u32 nvl_link_config_link_en_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 nvl_link_config_link_en_v(u32 r)
 {
@@ -270,7 +272,7 @@ static inline u32 nvl_link_change_oldstate_mask_f(u32 v)
 }
 static inline u32 nvl_link_change_oldstate_mask_m(void)
 {
-	return 0xfU << 16U;
+	return U32(0xfU) << 16U;
 }
 static inline u32 nvl_link_change_oldstate_mask_v(u32 r)
 {
@@ -290,7 +292,7 @@ static inline u32 nvl_link_change_newstate_f(u32 v)
 }
 static inline u32 nvl_link_change_newstate_m(void)
 {
-	return 0xfU << 4U;
+	return U32(0xfU) << 4U;
 }
 static inline u32 nvl_link_change_newstate_v(u32 r)
 {
@@ -326,7 +328,7 @@ static inline u32 nvl_link_change_action_f(u32 v)
 }
 static inline u32 nvl_link_change_action_m(void)
 {
-	return 0x3U << 2U;
+	return U32(0x3U) << 2U;
 }
 static inline u32 nvl_link_change_action_v(u32 r)
 {
@@ -346,7 +348,7 @@ static inline u32 nvl_link_change_status_f(u32 v)
 }
 static inline u32 nvl_link_change_status_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 nvl_link_change_status_v(u32 r)
 {
@@ -386,7 +388,7 @@ static inline u32 nvl_sublink_change_countdown_f(u32 v)
 }
 static inline u32 nvl_sublink_change_countdown_m(void)
 {
-	return 0xfffU << 20U;
+	return U32(0xfffU) << 20U;
 }
 static inline u32 nvl_sublink_change_countdown_v(u32 r)
 {
@@ -398,7 +400,7 @@ static inline u32 nvl_sublink_change_oldstate_mask_f(u32 v)
 }
 static inline u32 nvl_sublink_change_oldstate_mask_m(void)
 {
-	return 0xfU << 16U;
+	return U32(0xfU) << 16U;
 }
 static inline u32 nvl_sublink_change_oldstate_mask_v(u32 r)
 {
@@ -418,7 +420,7 @@ static inline u32 nvl_sublink_change_sublink_f(u32 v)
 }
 static inline u32 nvl_sublink_change_sublink_m(void)
 {
-	return 0xfU << 12U;
+	return U32(0xfU) << 12U;
 }
 static inline u32 nvl_sublink_change_sublink_v(u32 r)
 {
@@ -446,7 +448,7 @@ static inline u32 nvl_sublink_change_newstate_f(u32 v)
 }
 static inline u32 nvl_sublink_change_newstate_m(void)
 {
-	return 0xfU << 4U;
+	return U32(0xfU) << 4U;
 }
 static inline u32 nvl_sublink_change_newstate_v(u32 r)
 {
@@ -498,7 +500,7 @@ static inline u32 nvl_sublink_change_action_f(u32 v)
 }
 static inline u32 nvl_sublink_change_action_m(void)
 {
-	return 0x3U << 2U;
+	return U32(0x3U) << 2U;
 }
 static inline u32 nvl_sublink_change_action_v(u32 r)
 {
@@ -518,7 +520,7 @@ static inline u32 nvl_sublink_change_status_f(u32 v)
 }
 static inline u32 nvl_sublink_change_status_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 nvl_sublink_change_status_v(u32 r)
 {
@@ -558,7 +560,7 @@ static inline u32 nvl_link_test_mode_f(u32 v)
 }
 static inline u32 nvl_link_test_mode_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 nvl_link_test_mode_v(u32 r)
 {
@@ -578,7 +580,7 @@ static inline u32 nvl_link_test_auto_hwcfg_f(u32 v)
 }
 static inline u32 nvl_link_test_auto_hwcfg_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 nvl_link_test_auto_hwcfg_v(u32 r)
 {
@@ -598,7 +600,7 @@ static inline u32 nvl_link_test_auto_nvhs_f(u32 v)
 }
 static inline u32 nvl_link_test_auto_nvhs_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 nvl_link_test_auto_nvhs_v(u32 r)
 {
@@ -622,7 +624,7 @@ static inline u32 nvl_sl0_slsm_status_tx_substate_f(u32 v)
 }
 static inline u32 nvl_sl0_slsm_status_tx_substate_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 nvl_sl0_slsm_status_tx_substate_v(u32 r)
 {
@@ -634,7 +636,7 @@ static inline u32 nvl_sl0_slsm_status_tx_primary_state_f(u32 v)
 }
 static inline u32 nvl_sl0_slsm_status_tx_primary_state_m(void)
 {
-	return 0xfU << 4U;
+	return U32(0xfU) << 4U;
 }
 static inline u32 nvl_sl0_slsm_status_tx_primary_state_v(u32 r)
 {
@@ -690,7 +692,7 @@ static inline u32 nvl_sl1_slsm_status_rx_substate_f(u32 v)
 }
 static inline u32 nvl_sl1_slsm_status_rx_substate_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 nvl_sl1_slsm_status_rx_substate_v(u32 r)
 {
@@ -702,7 +704,7 @@ static inline u32 nvl_sl1_slsm_status_rx_primary_state_f(u32 v)
 }
 static inline u32 nvl_sl1_slsm_status_rx_primary_state_m(void)
 {
-	return 0xfU << 4U;
+	return U32(0xfU) << 4U;
 }
 static inline u32 nvl_sl1_slsm_status_rx_primary_state_v(u32 r)
 {
@@ -758,7 +760,7 @@ static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_f(u32 v)
 }
 static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_m(void)
 {
-	return 0x7ffU << 0U;
+	return U32(0x7ffU) << 0U;
 }
 static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_v(u32 r)
 {
@@ -778,7 +780,7 @@ static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(u32 v)
 }
 static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(void)
 {
-	return 0x1fU << 11U;
+	return U32(0x1fU) << 11U;
 }
 static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(u32 r)
 {
@@ -802,7 +804,7 @@ static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_f(u32 v)
 }
 static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_v(u32 r)
 {
@@ -814,7 +816,7 @@ static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_f(u32 v)
 }
 static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_m(void)
 {
-	return 0x7U << 16U;
+	return U32(0x7U) << 16U;
 }
 static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_v(u32 r)
 {
@@ -834,7 +836,7 @@ static inline u32 nvl_txiobist_configreg_io_bist_mode_in_f(u32 v)
 }
 static inline u32 nvl_txiobist_configreg_io_bist_mode_in_m(void)
 {
-	return 0x1U << 17U;
+	return U32(0x1U) << 17U;
 }
 static inline u32 nvl_txiobist_configreg_io_bist_mode_in_v(u32 r)
 {
@@ -850,7 +852,7 @@ static inline u32 nvl_txiobist_config_dpg_prbsseedld_f(u32 v)
 }
 static inline u32 nvl_txiobist_config_dpg_prbsseedld_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 nvl_txiobist_config_dpg_prbsseedld_v(u32 r)
 {
@@ -866,7 +868,7 @@ static inline u32 nvl_intr_tx_replay_f(u32 v)
 }
 static inline u32 nvl_intr_tx_replay_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 nvl_intr_tx_replay_v(u32 r)
 {
@@ -878,7 +880,7 @@ static inline u32 nvl_intr_tx_recovery_short_f(u32 v)
 }
 static inline u32 nvl_intr_tx_recovery_short_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 nvl_intr_tx_recovery_short_v(u32 r)
 {
@@ -890,7 +892,7 @@ static inline u32 nvl_intr_tx_recovery_long_f(u32 v)
 }
 static inline u32 nvl_intr_tx_recovery_long_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 nvl_intr_tx_recovery_long_v(u32 r)
 {
@@ -902,7 +904,7 @@ static inline u32 nvl_intr_tx_fault_ram_f(u32 v)
 }
 static inline u32 nvl_intr_tx_fault_ram_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 nvl_intr_tx_fault_ram_v(u32 r)
 {
@@ -914,7 +916,7 @@ static inline u32 nvl_intr_tx_fault_interface_f(u32 v)
 }
 static inline u32 nvl_intr_tx_fault_interface_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 nvl_intr_tx_fault_interface_v(u32 r)
 {
@@ -926,7 +928,7 @@ static inline u32 nvl_intr_tx_fault_sublink_change_f(u32 v)
 }
 static inline u32 nvl_intr_tx_fault_sublink_change_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 nvl_intr_tx_fault_sublink_change_v(u32 r)
 {
@@ -938,7 +940,7 @@ static inline u32 nvl_intr_rx_fault_sublink_change_f(u32 v)
 }
 static inline u32 nvl_intr_rx_fault_sublink_change_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 nvl_intr_rx_fault_sublink_change_v(u32 r)
 {
@@ -950,7 +952,7 @@ static inline u32 nvl_intr_rx_fault_dl_protocol_f(u32 v)
 }
 static inline u32 nvl_intr_rx_fault_dl_protocol_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 nvl_intr_rx_fault_dl_protocol_v(u32 r)
 {
@@ -962,7 +964,7 @@ static inline u32 nvl_intr_rx_short_error_rate_f(u32 v)
 }
 static inline u32 nvl_intr_rx_short_error_rate_m(void)
 {
-	return 0x1U << 21U;
+	return U32(0x1U) << 21U;
 }
 static inline u32 nvl_intr_rx_short_error_rate_v(u32 r)
 {
@@ -974,7 +976,7 @@ static inline u32 nvl_intr_rx_long_error_rate_f(u32 v)
 }
 static inline u32 nvl_intr_rx_long_error_rate_m(void)
 {
-	return 0x1U << 22U;
+	return U32(0x1U) << 22U;
 }
 static inline u32 nvl_intr_rx_long_error_rate_v(u32 r)
 {
@@ -986,7 +988,7 @@ static inline u32 nvl_intr_rx_ila_trigger_f(u32 v)
 }
 static inline u32 nvl_intr_rx_ila_trigger_m(void)
 {
-	return 0x1U << 23U;
+	return U32(0x1U) << 23U;
 }
 static inline u32 nvl_intr_rx_ila_trigger_v(u32 r)
 {
@@ -998,7 +1000,7 @@ static inline u32 nvl_intr_rx_crc_counter_f(u32 v)
 }
 static inline u32 nvl_intr_rx_crc_counter_m(void)
 {
-	return 0x1U << 24U;
+	return U32(0x1U) << 24U;
 }
 static inline u32 nvl_intr_rx_crc_counter_v(u32 r)
 {
@@ -1010,7 +1012,7 @@ static inline u32 nvl_intr_ltssm_fault_f(u32 v)
 }
 static inline u32 nvl_intr_ltssm_fault_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 nvl_intr_ltssm_fault_v(u32 r)
 {
@@ -1022,7 +1024,7 @@ static inline u32 nvl_intr_ltssm_protocol_f(u32 v)
 }
 static inline u32 nvl_intr_ltssm_protocol_m(void)
 {
-	return 0x1U << 29U;
+	return U32(0x1U) << 29U;
 }
 static inline u32 nvl_intr_ltssm_protocol_v(u32 r)
 {
@@ -1034,7 +1036,7 @@ static inline u32 nvl_intr_minion_request_f(u32 v)
 }
 static inline u32 nvl_intr_minion_request_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 nvl_intr_minion_request_v(u32 r)
 {
@@ -1054,7 +1056,7 @@ static inline u32 nvl_intr_minion_tx_replay_f(u32 v)
 }
 static inline u32 nvl_intr_minion_tx_replay_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 nvl_intr_minion_tx_replay_v(u32 r)
 {
@@ -1066,7 +1068,7 @@ static inline u32 nvl_intr_minion_tx_recovery_short_f(u32 v)
 }
 static inline u32 nvl_intr_minion_tx_recovery_short_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 nvl_intr_minion_tx_recovery_short_v(u32 r)
 {
@@ -1078,7 +1080,7 @@ static inline u32 nvl_intr_minion_tx_recovery_long_f(u32 v)
 }
 static inline u32 nvl_intr_minion_tx_recovery_long_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 nvl_intr_minion_tx_recovery_long_v(u32 r)
 {
@@ -1090,7 +1092,7 @@ static inline u32 nvl_intr_minion_tx_fault_ram_f(u32 v)
 }
 static inline u32 nvl_intr_minion_tx_fault_ram_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 nvl_intr_minion_tx_fault_ram_v(u32 r)
 {
@@ -1102,7 +1104,7 @@ static inline u32 nvl_intr_minion_tx_fault_interface_f(u32 v)
 }
 static inline u32 nvl_intr_minion_tx_fault_interface_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 nvl_intr_minion_tx_fault_interface_v(u32 r)
 {
@@ -1114,7 +1116,7 @@ static inline u32 nvl_intr_minion_tx_fault_sublink_change_f(u32 v)
 }
 static inline u32 nvl_intr_minion_tx_fault_sublink_change_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 nvl_intr_minion_tx_fault_sublink_change_v(u32 r)
 {
@@ -1126,7 +1128,7 @@ static inline u32 nvl_intr_minion_rx_fault_sublink_change_f(u32 v)
 }
 static inline u32 nvl_intr_minion_rx_fault_sublink_change_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 nvl_intr_minion_rx_fault_sublink_change_v(u32 r)
 {
@@ -1138,7 +1140,7 @@ static inline u32 nvl_intr_minion_rx_fault_dl_protocol_f(u32 v)
 }
 static inline u32 nvl_intr_minion_rx_fault_dl_protocol_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 nvl_intr_minion_rx_fault_dl_protocol_v(u32 r)
 {
@@ -1150,7 +1152,7 @@ static inline u32 nvl_intr_minion_rx_short_error_rate_f(u32 v)
 }
 static inline u32 nvl_intr_minion_rx_short_error_rate_m(void)
 {
-	return 0x1U << 21U;
+	return U32(0x1U) << 21U;
 }
 static inline u32 nvl_intr_minion_rx_short_error_rate_v(u32 r)
 {
@@ -1162,7 +1164,7 @@ static inline u32 nvl_intr_minion_rx_long_error_rate_f(u32 v)
 }
 static inline u32 nvl_intr_minion_rx_long_error_rate_m(void)
 {
-	return 0x1U << 22U;
+	return U32(0x1U) << 22U;
 }
 static inline u32 nvl_intr_minion_rx_long_error_rate_v(u32 r)
 {
@@ -1174,7 +1176,7 @@ static inline u32 nvl_intr_minion_rx_ila_trigger_f(u32 v)
 }
 static inline u32 nvl_intr_minion_rx_ila_trigger_m(void)
 {
-	return 0x1U << 23U;
+	return U32(0x1U) << 23U;
 }
 static inline u32 nvl_intr_minion_rx_ila_trigger_v(u32 r)
 {
@@ -1186,7 +1188,7 @@ static inline u32 nvl_intr_minion_rx_crc_counter_f(u32 v)
 }
 static inline u32 nvl_intr_minion_rx_crc_counter_m(void)
 {
-	return 0x1U << 24U;
+	return U32(0x1U) << 24U;
 }
 static inline u32 nvl_intr_minion_rx_crc_counter_v(u32 r)
 {
@@ -1198,7 +1200,7 @@ static inline u32 nvl_intr_minion_ltssm_fault_f(u32 v)
 }
 static inline u32 nvl_intr_minion_ltssm_fault_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 nvl_intr_minion_ltssm_fault_v(u32 r)
 {
@@ -1210,7 +1212,7 @@ static inline u32 nvl_intr_minion_ltssm_protocol_f(u32 v)
 }
 static inline u32 nvl_intr_minion_ltssm_protocol_m(void)
 {
-	return 0x1U << 29U;
+	return U32(0x1U) << 29U;
 }
 static inline u32 nvl_intr_minion_ltssm_protocol_v(u32 r)
 {
@@ -1222,7 +1224,7 @@ static inline u32 nvl_intr_minion_minion_request_f(u32 v)
 }
 static inline u32 nvl_intr_minion_minion_request_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 nvl_intr_minion_minion_request_v(u32 r)
 {
@@ -1242,7 +1244,7 @@ static inline u32 nvl_intr_stall_en_tx_replay_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_tx_replay_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 nvl_intr_stall_en_tx_replay_v(u32 r)
 {
@@ -1254,7 +1256,7 @@ static inline u32 nvl_intr_stall_en_tx_recovery_short_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_tx_recovery_short_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 nvl_intr_stall_en_tx_recovery_short_v(u32 r)
 {
@@ -1274,7 +1276,7 @@ static inline u32 nvl_intr_stall_en_tx_recovery_long_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_tx_recovery_long_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 nvl_intr_stall_en_tx_recovery_long_v(u32 r)
 {
@@ -1294,7 +1296,7 @@ static inline u32 nvl_intr_stall_en_tx_fault_ram_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_tx_fault_ram_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 nvl_intr_stall_en_tx_fault_ram_v(u32 r)
 {
@@ -1314,7 +1316,7 @@ static inline u32 nvl_intr_stall_en_tx_fault_interface_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_tx_fault_interface_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 nvl_intr_stall_en_tx_fault_interface_v(u32 r)
 {
@@ -1334,7 +1336,7 @@ static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_v(u32 r)
 {
@@ -1354,7 +1356,7 @@ static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_v(u32 r)
 {
@@ -1374,7 +1376,7 @@ static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_v(u32 r)
 {
@@ -1394,7 +1396,7 @@ static inline u32 nvl_intr_stall_en_rx_short_error_rate_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_rx_short_error_rate_m(void)
 {
-	return 0x1U << 21U;
+	return U32(0x1U) << 21U;
 }
 static inline u32 nvl_intr_stall_en_rx_short_error_rate_v(u32 r)
 {
@@ -1414,7 +1416,7 @@ static inline u32 nvl_intr_stall_en_rx_long_error_rate_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_rx_long_error_rate_m(void)
 {
-	return 0x1U << 22U;
+	return U32(0x1U) << 22U;
 }
 static inline u32 nvl_intr_stall_en_rx_long_error_rate_v(u32 r)
 {
@@ -1434,7 +1436,7 @@ static inline u32 nvl_intr_stall_en_rx_ila_trigger_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_rx_ila_trigger_m(void)
 {
-	return 0x1U << 23U;
+	return U32(0x1U) << 23U;
 }
 static inline u32 nvl_intr_stall_en_rx_ila_trigger_v(u32 r)
 {
@@ -1454,7 +1456,7 @@ static inline u32 nvl_intr_stall_en_rx_crc_counter_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_rx_crc_counter_m(void)
 {
-	return 0x1U << 24U;
+	return U32(0x1U) << 24U;
 }
 static inline u32 nvl_intr_stall_en_rx_crc_counter_v(u32 r)
 {
@@ -1474,7 +1476,7 @@ static inline u32 nvl_intr_stall_en_ltssm_fault_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_ltssm_fault_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 nvl_intr_stall_en_ltssm_fault_v(u32 r)
 {
@@ -1494,7 +1496,7 @@ static inline u32 nvl_intr_stall_en_ltssm_protocol_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_ltssm_protocol_m(void)
 {
-	return 0x1U << 29U;
+	return U32(0x1U) << 29U;
 }
 static inline u32 nvl_intr_stall_en_ltssm_protocol_v(u32 r)
 {
@@ -1514,7 +1516,7 @@ static inline u32 nvl_intr_stall_en_minion_request_f(u32 v)
 }
 static inline u32 nvl_intr_stall_en_minion_request_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 nvl_intr_stall_en_minion_request_v(u32 r)
 {
@@ -1538,7 +1540,7 @@ static inline u32 nvl_br0_cfg_cal_rxcal_f(u32 v)
 }
 static inline u32 nvl_br0_cfg_cal_rxcal_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 nvl_br0_cfg_cal_rxcal_v(u32 r)
 {
@@ -1562,7 +1564,7 @@ static inline u32 nvl_br0_cfg_status_cal_rxcal_done_f(u32 v)
 }
 static inline u32 nvl_br0_cfg_status_cal_rxcal_done_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 nvl_br0_cfg_status_cal_rxcal_done_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h
index 217c3aece..cf7c38542 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_NVLINKIP_DISCOVERY_GV100_H
 #define NVGPU_HW_NVLINKIP_DISCOVERY_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 nvlinkip_discovery_common_r(void)
 {
 	return 0x00000000U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h
index 895bc4a3d..2387a0240 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_NVLIPT_GV100_H
 #define NVGPU_HW_NVLIPT_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 nvlipt_intr_control_link0_r(void)
 {
 	return 0x000004b4U;
@@ -66,7 +68,7 @@ static inline u32 nvlipt_intr_control_link0_stallenable_f(u32 v)
 }
 static inline u32 nvlipt_intr_control_link0_stallenable_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 nvlipt_intr_control_link0_stallenable_v(u32 r)
 {
@@ -78,7 +80,7 @@ static inline u32 nvlipt_intr_control_link0_nostallenable_f(u32 v)
 }
 static inline u32 nvlipt_intr_control_link0_nostallenable_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 nvlipt_intr_control_link0_nostallenable_v(u32 r)
 {
@@ -214,7 +216,7 @@ static inline u32 nvlipt_err_control_link0_fatalenable_f(u32 v)
 }
 static inline u32 nvlipt_err_control_link0_fatalenable_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 nvlipt_err_control_link0_fatalenable_v(u32 r)
 {
@@ -226,7 +228,7 @@ static inline u32 nvlipt_err_control_link0_nonfatalenable_f(u32 v)
 }
 static inline u32 nvlipt_err_control_link0_nonfatalenable_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 nvlipt_err_control_link0_nonfatalenable_v(u32 r)
 {
@@ -242,7 +244,7 @@ static inline u32 nvlipt_intr_control_common_stallenable_f(u32 v)
 }
 static inline u32 nvlipt_intr_control_common_stallenable_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 nvlipt_intr_control_common_stallenable_v(u32 r)
 {
@@ -254,7 +256,7 @@ static inline u32 nvlipt_intr_control_common_nonstallenable_f(u32 v)
 }
 static inline u32 nvlipt_intr_control_common_nonstallenable_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 nvlipt_intr_control_common_nonstallenable_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h
index 76c4e16b7..9c23ae73b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_NVTLC_GV100_H
 #define NVGPU_HW_NVTLC_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 nvtlc_tx_err_report_en_0_r(void)
 {
 	return 0x00000708U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
index bb0eff0b3..7ca487a05 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PBDMA_GV100_H
 #define NVGPU_HW_PBDMA_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pbdma_gp_entry1_r(void)
 {
 	return 0x10000004U;
@@ -514,7 +516,7 @@ static inline u32 pbdma_intr_1_r(u32 i)
 }
 static inline u32 pbdma_intr_1_ctxnotvalid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void)
 {
@@ -638,7 +640,7 @@ static inline u32 pbdma_timeout_r(u32 i)
 }
 static inline u32 pbdma_timeout_period_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 pbdma_timeout_period_max_f(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
index e643d11f6..84455b5de 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PERF_GV100_H
 #define NVGPU_HW_PERF_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 perf_pmmgpc_perdomain_offset_v(void)
 {
 	return 0x00000200U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h
index 86eed69c3..71026ca88 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PGSP_GV100_H
 #define NVGPU_HW_PGSP_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pgsp_falcon_irqsset_r(void)
 {
 	return 0x00110000U;
@@ -330,7 +332,7 @@ static inline u32 pgsp_falcon_cpuctl_halt_intr_f(u32 v)
 }
 static inline u32 pgsp_falcon_cpuctl_halt_intr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 pgsp_falcon_cpuctl_halt_intr_v(u32 r)
 {
@@ -342,7 +344,7 @@ static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 }
 static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
 {
@@ -402,11 +404,11 @@ static inline u32 pgsp_falcon_dmactl_r(void)
 }
 static inline u32 pgsp_falcon_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 pgsp_falcon_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pgsp_falcon_dmactl_require_ctx_f(u32 v)
 {
@@ -470,7 +472,7 @@ static inline u32 pgsp_falcon_exterrstat_r(void)
 }
 static inline u32 pgsp_falcon_exterrstat_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 pgsp_falcon_exterrstat_valid_v(u32 r)
 {
@@ -494,7 +496,7 @@ static inline u32 pgsp_sec2_falcon_icd_cmd_opc_f(u32 v)
 }
 static inline u32 pgsp_sec2_falcon_icd_cmd_opc_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 pgsp_sec2_falcon_icd_cmd_opc_v(u32 r)
 {
@@ -526,7 +528,7 @@ static inline u32 pgsp_falcon_dmemc_offs_f(u32 v)
 }
 static inline u32 pgsp_falcon_dmemc_offs_m(void)
 {
-	return 0x3fU << 2U;
+	return U32(0x3fU) << 2U;
 }
 static inline u32 pgsp_falcon_dmemc_blk_f(u32 v)
 {
@@ -534,7 +536,7 @@ static inline u32 pgsp_falcon_dmemc_blk_f(u32 v)
 }
 static inline u32 pgsp_falcon_dmemc_blk_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 pgsp_falcon_dmemc_aincw_f(u32 v)
 {
@@ -562,7 +564,7 @@ static inline u32 pgsp_falcon_debug1_ctxsw_mode_f(u32 v)
 }
 static inline u32 pgsp_falcon_debug1_ctxsw_mode_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 pgsp_falcon_debug1_ctxsw_mode_v(u32 r)
 {
@@ -598,7 +600,7 @@ static inline u32 pgsp_fbif_transcfg_mem_type_f(u32 v)
 }
 static inline u32 pgsp_fbif_transcfg_mem_type_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pgsp_fbif_transcfg_mem_type_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h
index 23d535332..58ec25a7b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PRAM_GV100_H
 #define NVGPU_HW_PRAM_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pram_data032_r(u32 i)
 {
 	return 0x00700000U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h
index 0554acf64..990760501 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h
@@ -56,13 +56,15 @@
 #ifndef NVGPU_HW_PRI_RINGMASTER_GV100_H
 #define NVGPU_HW_PRI_RINGMASTER_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pri_ringmaster_command_r(void)
 {
 	return 0x0012004cU;
 }
 static inline u32 pri_ringmaster_command_cmd_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 pri_ringmaster_command_cmd_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h
index 36051c618..4bba189d3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PRI_RINGSTATION_GPC_GV100_H
 #define NVGPU_HW_PRI_RINGSTATION_GPC_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
 {
 	return 0x00128300U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h
index 51a34528d..31cf7aeb7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PRI_RINGSTATION_SYS_GV100_H
 #define NVGPU_HW_PRI_RINGSTATION_SYS_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pri_ringstation_sys_master_config_r(u32 i)
 {
 	return 0x00122300U + i*4U;
@@ -66,7 +68,7 @@ static inline u32 pri_ringstation_sys_decode_config_r(void)
 }
 static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h
index ddb413403..0fa1327aa 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PROJ_GV100_H
 #define NVGPU_HW_PROJ_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 proj_gpc_base_v(void)
 {
 	return 0x00500000U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
index c77907074..86190e117 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PWR_GV100_H
 #define NVGPU_HW_PWR_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pwr_falcon_irqsset_r(void)
 {
 	return 0x0010a000U;
@@ -406,7 +408,7 @@ static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
 }
 static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
 {
@@ -418,7 +420,7 @@ static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 }
 static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
 {
@@ -442,7 +444,7 @@ static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
 }
 static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
 {
@@ -494,11 +496,11 @@ static inline u32 pwr_falcon_dmactl_r(void)
 }
 static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pwr_falcon_hwcfg_r(void)
 {
@@ -558,7 +560,7 @@ static inline u32 pwr_falcon_exterrstat_r(void)
 }
 static inline u32 pwr_falcon_exterrstat_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
 {
@@ -582,7 +584,7 @@ static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
 {
@@ -614,7 +616,7 @@ static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
 }
 static inline u32 pwr_falcon_dmemc_offs_m(void)
 {
-	return 0x3fU << 2U;
+	return U32(0x3fU) << 2U;
 }
 static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
 {
@@ -622,7 +624,7 @@ static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
 }
 static inline u32 pwr_falcon_dmemc_blk_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
 {
@@ -686,7 +688,7 @@ static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
 }
 static inline u32 pwr_pmu_mutex_id_release_value_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
 {
@@ -806,7 +808,7 @@ static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
 }
 static inline u32 pwr_pmu_idle_ctrl_value_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
 {
@@ -818,7 +820,7 @@ static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
 }
 static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
 {
@@ -918,7 +920,7 @@ static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
 }
 static inline u32 pwr_fbif_transcfg_mem_type_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h
index b0da9caa0..1ccae1464 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_RAM_GV100_H
 #define NVGPU_HW_RAM_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ram_in_ramfc_s(void)
 {
 	return 4096U;
@@ -102,7 +104,7 @@ static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
 }
 static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
 {
@@ -118,7 +120,7 @@ static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
 }
 static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
 {
@@ -134,7 +136,7 @@ static inline u32 ram_in_use_ver2_pt_format_f(u32 v)
 }
 static inline u32 ram_in_use_ver2_pt_format_m(void)
 {
-	return 0x1U << 10U;
+	return U32(0x1U) << 10U;
 }
 static inline u32 ram_in_use_ver2_pt_format_w(void)
 {
@@ -154,7 +156,7 @@ static inline u32 ram_in_big_page_size_f(u32 v)
 }
 static inline u32 ram_in_big_page_size_m(void)
 {
-	return 0x1U << 11U;
+	return U32(0x1U) << 11U;
 }
 static inline u32 ram_in_big_page_size_w(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h
index be6a39118..becf8227b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_THERM_GV100_H
 #define NVGPU_HW_THERM_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 therm_weight_1_r(void)
 {
 	return 0x00020024U;
@@ -82,7 +84,7 @@ static inline u32 therm_gate_ctrl_r(u32 i)
 }
 static inline u32 therm_gate_ctrl_eng_clk_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
 {
@@ -98,7 +100,7 @@ static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
 }
 static inline u32 therm_gate_ctrl_blk_clk_m(void)
 {
-	return 0x3U << 2U;
+	return U32(0x3U) << 2U;
 }
 static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
 {
@@ -110,7 +112,7 @@ static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
 }
 static inline u32 therm_gate_ctrl_idle_holdoff_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void)
 {
@@ -126,7 +128,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
 {
-	return 0x1fU << 8U;
+	return U32(0x1fU) << 8U;
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
 {
@@ -134,7 +136,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
 {
-	return 0x7U << 13U;
+	return U32(0x7U) << 13U;
 }
 static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
 {
@@ -142,7 +144,7 @@ static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
 {
-	return 0xfU << 16U;
+	return U32(0xfU) << 16U;
 }
 static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
 {
@@ -150,7 +152,7 @@ static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
 {
-	return 0xfU << 20U;
+	return U32(0xfU) << 20U;
 }
 static inline u32 therm_fecs_idle_filter_r(void)
 {
@@ -158,7 +160,7 @@ static inline u32 therm_fecs_idle_filter_r(void)
 }
 static inline u32 therm_fecs_idle_filter_value_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 therm_hubmmu_idle_filter_r(void)
 {
@@ -166,7 +168,7 @@ static inline u32 therm_hubmmu_idle_filter_r(void)
 }
 static inline u32 therm_hubmmu_idle_filter_value_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 therm_clk_slowdown_r(u32 i)
 {
@@ -178,7 +180,7 @@ static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
 }
 static inline u32 therm_clk_slowdown_idle_factor_m(void)
 {
-	return 0x3fU << 16U;
+	return U32(0x3fU) << 16U;
 }
 static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
 {
@@ -198,7 +200,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
 {
@@ -222,7 +224,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
 {
-	return 0x3fU << 6U;
+	return U32(0x3fU) << 6U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
 {
@@ -230,7 +232,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
 {
-	return 0x3fU << 12U;
+	return U32(0x3fU) << 12U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
 {
@@ -238,7 +240,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
 {
-	return 0x3fU << 18U;
+	return U32(0x3fU) << 18U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
 {
@@ -246,7 +248,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
 {
-	return 0x3fU << 24U;
+	return U32(0x3fU) << 24U;
 }
 static inline u32 therm_grad_stepping0_r(void)
 {
@@ -262,7 +264,7 @@ static inline u32 therm_grad_stepping0_feature_f(u32 v)
 }
 static inline u32 therm_grad_stepping0_feature_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 therm_grad_stepping0_feature_v(u32 r)
 {
@@ -290,7 +292,7 @@ static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
 }
 static inline u32 therm_clk_timing_grad_slowdown_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h
index a530764a6..21fef5ea6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_TIMER_GV100_H
 #define NVGPU_HW_TIMER_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 timer_pri_timeout_r(void)
 {
 	return 0x00009080U;
@@ -66,7 +68,7 @@ static inline u32 timer_pri_timeout_period_f(u32 v)
 }
 static inline u32 timer_pri_timeout_period_m(void)
 {
-	return 0xffffffU << 0U;
+	return U32(0xffffffU) << 0U;
 }
 static inline u32 timer_pri_timeout_period_v(u32 r)
 {
@@ -78,7 +80,7 @@ static inline u32 timer_pri_timeout_en_f(u32 v)
 }
 static inline u32 timer_pri_timeout_en_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 timer_pri_timeout_en_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h
index 601ade9c0..49c5c5eff 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_TOP_GV100_H
 #define NVGPU_HW_TOP_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 top_num_gpcs_r(void)
 {
 	return 0x00022430U;
@@ -266,7 +268,7 @@ static inline u32 top_nvhsclk_ctrl_e_clk_nvl_f(u32 v)
 }
 static inline u32 top_nvhsclk_ctrl_e_clk_nvl_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 top_nvhsclk_ctrl_e_clk_nvl_v(u32 r)
 {
@@ -278,7 +280,7 @@ static inline u32 top_nvhsclk_ctrl_e_clk_pcie_f(u32 v)
 }
 static inline u32 top_nvhsclk_ctrl_e_clk_pcie_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 top_nvhsclk_ctrl_e_clk_pcie_v(u32 r)
 {
@@ -290,7 +292,7 @@ static inline u32 top_nvhsclk_ctrl_e_clk_core_f(u32 v)
 }
 static inline u32 top_nvhsclk_ctrl_e_clk_core_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 top_nvhsclk_ctrl_e_clk_core_v(u32 r)
 {
@@ -302,7 +304,7 @@ static inline u32 top_nvhsclk_ctrl_rfu_f(u32 v)
 }
 static inline u32 top_nvhsclk_ctrl_rfu_m(void)
 {
-	return 0xfU << 5U;
+	return U32(0xfU) << 5U;
 }
 static inline u32 top_nvhsclk_ctrl_rfu_v(u32 r)
 {
@@ -314,7 +316,7 @@ static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_f(u32 v)
 }
 static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_m(void)
 {
-	return 0x7U << 10U;
+	return U32(0x7U) << 10U;
 }
 static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_v(u32 r)
 {
@@ -326,7 +328,7 @@ static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_f(u32 v)
 }
 static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_m(void)
 {
-	return 0x1U << 9U;
+	return U32(0x1U) << 9U;
 }
 static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_v(u32 r)
 {
@@ -338,7 +340,7 @@ static inline u32 top_nvhsclk_ctrl_swap_clk_core_f(u32 v)
 }
 static inline u32 top_nvhsclk_ctrl_swap_clk_core_m(void)
 {
-	return 0x1U << 13U;
+	return U32(0x1U) << 13U;
 }
 static inline u32 top_nvhsclk_ctrl_swap_clk_core_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h
index 58300c9f6..f9aa0e7e4 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_TRIM_GV100_H
 #define NVGPU_HW_TRIM_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 trim_sys_nvlink_uphy_cfg_r(void)
 {
 	return 0x00132410U;
@@ -66,7 +68,7 @@ static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(u32 v)
 }
 static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m(void)
 {
-	return 0x3ffU << 0U;
+	return U32(0x3ffU) << 0U;
 }
 static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(u32 r)
 {
@@ -78,7 +80,7 @@ static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(u32 v)
 }
 static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m(void)
 {
-	return 0x1U << 12U;
+	return U32(0x1U) << 12U;
 }
 static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(u32 r)
 {
@@ -90,7 +92,7 @@ static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(u32 v)
 }
 static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m(void)
 {
-	return 0xffU << 16U;
+	return U32(0xffU) << 16U;
 }
 static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(u32 r)
 {
@@ -106,7 +108,7 @@ static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(u32 v)
 }
 static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(u32 r)
 {
@@ -122,7 +124,7 @@ static inline u32 trim_sys_nvlink0_status_pll_off_f(u32 v)
 }
 static inline u32 trim_sys_nvlink0_status_pll_off_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 trim_sys_nvlink0_status_pll_off_v(u32 r)
 {
@@ -138,7 +140,7 @@ static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_f(u32 v)
 }
 static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_m(void)
 {
-	return 0x3U << 16U;
+	return U32(0x3U) << 16U;
 }
 static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_v(u32 r)
 {
@@ -166,7 +168,7 @@ static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_f(u32 v)
 }
 static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h
index 3703dad16..01ec4f3ed 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_USERMODE_GV100_H
 #define NVGPU_HW_USERMODE_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 usermode_cfg0_r(void)
 {
 	return 0x00810000U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h
index b9b28a258..c6c942f25 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_XP_GV100_H
 #define NVGPU_HW_XP_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 xp_dl_mgr_r(u32 i)
 {
 	return 0x0008b8c0U + i*4U;
@@ -82,7 +84,7 @@ static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v)
 }
 static inline u32 xp_pl_link_config_ltssm_directive_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void)
 {
@@ -98,7 +100,7 @@ static inline u32 xp_pl_link_config_max_link_rate_f(u32 v)
 }
 static inline u32 xp_pl_link_config_max_link_rate_m(void)
 {
-	return 0x3U << 18U;
+	return U32(0x3U) << 18U;
 }
 static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void)
 {
@@ -118,7 +120,7 @@ static inline u32 xp_pl_link_config_target_tx_width_f(u32 v)
 }
 static inline u32 xp_pl_link_config_target_tx_width_m(void)
 {
-	return 0x7U << 20U;
+	return U32(0x7U) << 20U;
 }
 static inline u32 xp_pl_link_config_target_tx_width_x1_v(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h
index 7b3ad39f2..7d45b1360 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_XVE_GV100_H
 #define NVGPU_HW_XVE_GV100_H
 
+#include <nvgpu/types.h>
+
 static inline u32 xve_rom_ctrl_r(void)
 {
 	return 0x00000050U;
@@ -78,7 +80,7 @@ static inline u32 xve_link_control_status_r(void)
 }
 static inline u32 xve_link_control_status_link_speed_m(void)
 {
-	return 0xfU << 16U;
+	return U32(0xfU) << 16U;
 }
 static inline u32 xve_link_control_status_link_speed_v(u32 r)
 {
@@ -98,7 +100,7 @@ static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void)
 }
 static inline u32 xve_link_control_status_link_width_m(void)
 {
-	return 0x3fU << 20U;
+	return U32(0x3fU) << 20U;
 }
 static inline u32 xve_link_control_status_link_width_v(u32 r)
 {
@@ -134,7 +136,7 @@ static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v)
 }
 static inline u32 xve_priv_xv_cya_l0s_enable_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r)
 {
@@ -146,7 +148,7 @@ static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v)
 }
 static inline u32 xve_priv_xv_cya_l1_enable_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r)
 {
@@ -162,15 +164,15 @@ static inline u32 xve_reset_r(void)
 }
 static inline u32 xve_reset_reset_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 xve_reset_gpu_on_sw_reset_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 xve_reset_counter_en_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 xve_reset_counter_val_f(u32 v)
 {
@@ -178,7 +180,7 @@ static inline u32 xve_reset_counter_val_f(u32 v)
 }
 static inline u32 xve_reset_counter_val_m(void)
 {
-	return 0x7ffU << 4U;
+	return U32(0x7ffU) << 4U;
 }
 static inline u32 xve_reset_counter_val_v(u32 r)
 {
@@ -186,11 +188,11 @@ static inline u32 xve_reset_counter_val_v(u32 r)
 }
 static inline u32 xve_reset_clock_on_sw_reset_m(void)
 {
-	return 0x1U << 15U;
+	return U32(0x1U) << 15U;
 }
 static inline u32 xve_reset_clock_counter_en_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 xve_reset_clock_counter_val_f(u32 v)
 {
@@ -198,7 +200,7 @@ static inline u32 xve_reset_clock_counter_val_f(u32 v)
 }
 static inline u32 xve_reset_clock_counter_val_m(void)
 {
-	return 0x7ffU << 17U;
+	return U32(0x7ffU) << 17U;
 }
 static inline u32 xve_reset_clock_counter_val_v(u32 r)
 {