From c961b7ed1dc30d860ae5bfb22460cdc4c8d8d68e Mon Sep 17 00:00:00 2001 From: Adeel Raza Date: Fri, 28 Dec 2018 14:42:08 -0800 Subject: [PATCH] nvgpu: fifo: fix invalid ID macros MISRA rule 10.1 prohibits using signed values with bitwise operators. Make fifo invalid ID macros compliant with this MISRA rule. Also use these macros in source code instead of hardcoded numbers to make the code more readable. JIRA NVGPU-1006 Change-Id: I2f336d1decbc53b08f93587f2e00ea2cce47f72b Signed-off-by: Adeel Raza Reviewed-on: https://git-master.nvidia.com/r/1983700 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/channel.c | 12 ++++++++++-- drivers/gpu/nvgpu/common/fifo/tsg.c | 8 ++++++-- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 6 +++++- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 11 ++++++----- drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 4 ++-- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 6 +++++- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 6 +++--- 7 files changed, 37 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index ceeea1995..f4102f763 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c @@ -2429,7 +2429,11 @@ int gk20a_channel_suspend(struct gk20a *g) } if (channels_in_use) { - gk20a_fifo_update_runlist_ids(g, active_runlist_ids, ~0, false, true); + gk20a_fifo_update_runlist_ids(g, + active_runlist_ids, + FIFO_INVAL_CHANNEL_ID, + false, + true); for (chid = 0; chid < f->num_channels; chid++) { struct channel_gk20a *ch = gk20a_channel_from_id(g, chid); @@ -2479,7 +2483,11 @@ int gk20a_channel_resume(struct gk20a *g) } if (channels_in_use) { - gk20a_fifo_update_runlist_ids(g, active_runlist_ids, ~0, true, true); + gk20a_fifo_update_runlist_ids(g, + active_runlist_ids, + FIFO_INVAL_CHANNEL_ID, + true, + true); } nvgpu_log_fn(g, "done"); diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 4c06be49e..a6be232c3 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c @@ -382,7 +382,11 @@ int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level) break; } - return (ret != 0) ? ret : g->ops.fifo.update_runlist(g, tsg->runlist_id, ~0, true, true); + return (ret != 0) ? ret : g->ops.fifo.update_runlist(g, + tsg->runlist_id, + FIFO_INVAL_CHANNEL_ID, + true, + true); } int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) @@ -470,7 +474,7 @@ int gk20a_tsg_open_common(struct gk20a *g, struct tsg_gk20a *tsg) tsg->timeslice_us = 0; tsg->timeslice_timeout = 0; tsg->timeslice_scale = 0; - tsg->runlist_id = ~0u; + tsg->runlist_id = FIFO_INVAL_TSG_ID; tsg->sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; tsg->gr_ctx = nvgpu_kzalloc(g, sizeof(*tsg->gr_ctx)); if (tsg->gr_ctx == NULL) { diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 0a7a899c0..7419fe283 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -2834,7 +2834,11 @@ int gk20a_fifo_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) tsg->timeslice_us = timeslice; - return g->ops.fifo.update_runlist(g, tsg->runlist_id, ~0, true, true); + return g->ops.fifo.update_runlist(g, + tsg->runlist_id, + FIFO_INVAL_CHANNEL_ID, + true, + true); } void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id, diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 04d35f313..873b781e0 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -39,14 +39,15 @@ struct tsg_gk20a; #define MAX_RUNLIST_BUFFERS 2U -#define FIFO_INVAL_ENGINE_ID ((u32)~0) -#define FIFO_INVAL_CHANNEL_ID ((u32)~0) -#define FIFO_INVAL_TSG_ID ((u32)~0) -#define FIFO_INVAL_RUNLIST_ID ((u32)~0) +#define FIFO_INVAL_ENGINE_ID (~U32(0U)) +#define FIFO_INVAL_MMU_ID (~U32(0U)) +#define FIFO_INVAL_CHANNEL_ID (~U32(0U)) +#define FIFO_INVAL_TSG_ID (~U32(0U)) +#define FIFO_INVAL_RUNLIST_ID (~U32(0U)) #define ID_TYPE_CHANNEL 0U #define ID_TYPE_TSG 1U -#define ID_TYPE_UNKNOWN ((u32)~0) +#define ID_TYPE_UNKNOWN (~U32(0U)) #define RC_YES 1U #define RC_NO 0U diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index fb19c1df7..a27d77667 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -71,7 +71,7 @@ void channel_gm20b_bind(struct channel_gk20a *c) static inline u32 gm20b_engine_id_to_mmu_id(struct gk20a *g, u32 engine_id) { - u32 fault_id = ~0; + u32 fault_id = FIFO_INVAL_MMU_ID; struct fifo_engine_info_gk20a *engine_info; engine_info = gk20a_fifo_get_engine_info(g, engine_id); @@ -99,7 +99,7 @@ void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, } else { u32 mmu_id = gm20b_engine_id_to_mmu_id(g, engine_id); - if (mmu_id != (u32)~0) { + if (mmu_id != FIFO_INVAL_MMU_ID) { gk20a_writel(g, fifo_trigger_mmu_fault_r(mmu_id), fifo_trigger_mmu_fault_enable_f(1)); } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 3e988fbdf..f65d38222 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1616,7 +1616,11 @@ static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a return ret; } - ret = g->ops.fifo.update_runlist(g, fault_ch->runlist_id, ~0, true, false); + ret = g->ops.fifo.update_runlist(g, + fault_ch->runlist_id, + FIFO_INVAL_CHANNEL_ID, + true, + false); if (ret != 0) { nvgpu_err(g, "CILP: failed to restart runlist 0!"); diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index c229959de..0efa18ad8 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -1,7 +1,7 @@ /* * GV11B Fifo * - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,8 +27,8 @@ #define PBDMA_SUBDEVICE_ID 1U -#define FIFO_INVAL_PBDMA_ID ((u32)~0) -#define FIFO_INVAL_VEID ((u32)~0) +#define FIFO_INVAL_PBDMA_ID (~U32(0U)) +#define FIFO_INVAL_VEID (~U32(0U)) /* engine context-switch request occurred while the engine was in reset */ #define SCHED_ERROR_CODE_ENGINE_RESET 0x00000005U