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gpu: nvgpu: delete gp106/gr_gp106.c

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gp106 is not supported, and none of the API in this file is getting
re-used for other chips.
Hence delete this file and the header

Jira NVGPU-3112

Change-Id: Icc659bff254c084266407e7eb6b6c08b94134a33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096161
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-04-12 17:18:35 +05:30
committed by mobile promotions
parent 8188a3bd0d
commit c97fc81d21
6 changed files with 0 additions and 245 deletions
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1
drivers/gpu/nvgpu/Makefile
View File

@@ -547,7 +547,6 @@ nvgpu-y += \
gp10b/ce_gp10b.o \
gp10b/mm_gp10b.o \
gp10b/hal_gp10b.o \
gp106/gr_gp106.o \
gp106/bios_gp106.o \
gv11b/hal_gv11b.o \
gv11b/gr_gv11b.o \

1
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -262,7 +262,6 @@ srcs += common/sim.c \
gv11b/fifo_gv11b.c \
gv11b/mm_gv11b.c \
gv11b/ce_gv11b.c \
gp106/gr_gp106.c \
gp106/bios_gp106.c \
gp106/clk_gp106.c \
gv100/mm_gv100.c \

201
drivers/gpu/nvgpu/gp106/gr_gp106.c
View File

@@ -1,201 +0,0 @@
/*
* GP106 GPU GR
*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/class.h>
#include <nvgpu/dma.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/ctx.h>
#include <nvgpu/gr/config.h>
#include "gk20a/gr_gk20a.h"
#include "gm20b/gr_gm20b.h"
#include "gp10b/gr_gp10b.h"
#include <nvgpu/io.h>
#include "gr_gp106.h"
#include <nvgpu/hw/gp106/hw_gr_gp106.h>
u32 gr_gp106_pagepool_default_size(struct gk20a *g)
{
return gr_scc_pagepool_total_pages_hwmax_value_v();
}
static void gr_gp106_set_go_idle_timeout(struct gk20a *g, u32 data)
{
gk20a_writel(g, gr_fe_go_idle_timeout_r(), data);
}
int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data)
{
nvgpu_log_fn(g, " ");
if (class_num == PASCAL_COMPUTE_B) {
switch (offset << 2) {
case NVC0C0_SET_SHADER_EXCEPTIONS:
g->ops.gr.intr.set_shader_exceptions(g, data);
break;
case NVC0C0_SET_RD_COALESCE:
g->ops.gr.init.lg_coalesce(g, data);
break;
default:
goto fail;
}
}
if (class_num == PASCAL_B) {
switch (offset << 2) {
case NVC097_SET_SHADER_EXCEPTIONS:
g->ops.gr.intr.set_shader_exceptions(g, data);
break;
case NVC097_SET_CIRCULAR_BUFFER_SIZE:
g->ops.gr.set_circular_buffer_size(g, data);
break;
case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
g->ops.gr.set_alpha_circular_buffer_size(g, data);
break;
case NVC097_SET_GO_IDLE_TIMEOUT:
gr_gp106_set_go_idle_timeout(g, data);
break;
case NVC097_SET_RD_COALESCE:
g->ops.gr.init.lg_coalesce(g, data);
break;
case NVC097_SET_BES_CROP_DEBUG3:
g->ops.gr.set_bes_crop_debug3(g, data);
break;
case NVC097_SET_BES_CROP_DEBUG4:
g->ops.gr.set_bes_crop_debug4(g, data);
break;
default:
goto fail;
}
}
return 0;
fail:
return -EINVAL;
}
int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx,
struct vm_gk20a *vm, u32 class,
u32 graphics_preempt_mode,
u32 compute_preempt_mode)
{
int err = 0;
if (class == PASCAL_B && g->gr.ctx_vars.force_preemption_gfxp) {
graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
}
if (class == PASCAL_COMPUTE_B &&
g->gr.ctx_vars.force_preemption_cilp) {
compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
}
/* check for invalid combinations */
if ((graphics_preempt_mode == 0U) && (compute_preempt_mode == 0U)) {
return -EINVAL;
}
if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) &&
(compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) {
return -EINVAL;
}
/* set preemption modes */
switch (graphics_preempt_mode) {
case NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP:
{
u32 spill_size =
gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
u32 pagepool_size = g->ops.gr.init.pagepool_default_size(g) *
gr_scc_pagepool_total_pages_byte_granularity_v();
u32 betacb_size = g->ops.gr.init.get_attrib_cb_default_size(g) +
(gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
u32 alpha_cb_size = g->ops.gr.init.get_alpha_cb_size(g,
nvgpu_gr_config_get_tpc_count(g->gr.config));
u32 attrib_cb_size = (betacb_size + alpha_cb_size) *
gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
nvgpu_gr_config_get_max_tpc_count(g->gr.config);
attrib_cb_size = ALIGN(attrib_cb_size, 128);
nvgpu_log_info(g, "gfxp context spill_size=%d", spill_size);
nvgpu_log_info(g, "gfxp context pagepool_size=%d", pagepool_size);
nvgpu_log_info(g, "gfxp context attrib_cb_size=%d",
attrib_cb_size);
nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc,
NVGPU_GR_CTX_PREEMPT_CTXSW,
g->gr.ctx_vars.preempt_image_size);
nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc,
NVGPU_GR_CTX_SPILL_CTXSW, spill_size);
nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc,
NVGPU_GR_CTX_BETACB_CTXSW, attrib_cb_size);
nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc,
NVGPU_GR_CTX_PAGEPOOL_CTXSW, pagepool_size);
err = nvgpu_gr_ctx_alloc_ctxsw_buffers(g, gr_ctx,
g->gr.gr_ctx_desc, vm);
if (err != 0) {
nvgpu_err(g, "cannot allocate ctxsw buffers");
goto fail;
}
nvgpu_gr_ctx_init_graphics_preemption_mode(gr_ctx,
graphics_preempt_mode);
break;
}
case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI:
nvgpu_gr_ctx_init_graphics_preemption_mode(gr_ctx,
graphics_preempt_mode);
break;
default:
break;
}
if (class == PASCAL_COMPUTE_B) {
switch (compute_preempt_mode) {
case NVGPU_PREEMPTION_MODE_COMPUTE_WFI:
case NVGPU_PREEMPTION_MODE_COMPUTE_CTA:
case NVGPU_PREEMPTION_MODE_COMPUTE_CILP:
nvgpu_gr_ctx_init_compute_preemption_mode(gr_ctx,
compute_preempt_mode);
break;
default:
break;
}
}
return 0;
fail:
return err;
}

39
drivers/gpu/nvgpu/gp106/gr_gp106.h
View File

@@ -1,39 +0,0 @@
/*
* GP106 GPU GR
*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_GR_GP106_H
#define NVGPU_GR_GP106_H
struct gk20a;
u32 gr_gp106_pagepool_default_size(struct gk20a *g);
int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data);
int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx,
struct vm_gk20a *vm, u32 class,
u32 graphics_preempt_mode,
u32 compute_preempt_mode);
#endif /* NVGPU_GR_GP106_H */

1
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -138,7 +138,6 @@
#include "gm20b/mm_gm20b.h"
#include "gp106/bios_gp106.h"
#include "gp106/gr_gp106.h"
#include "gp10b/gr_gp10b.h"
#include "gp10b/ce_gp10b.h"

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -152,8 +152,6 @@
#include "gp106/bios_gp106.h"
#include "gp106/gr_gp106.h"
#include "gp10b/gr_gp10b.h"
#include "gp10b/ce_gp10b.h"
#include "gp10b/mm_gp10b.h"