diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
index 9c545f02e..13d9ff4a7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -766,6 +766,30 @@ static inline u32 pwr_pmu_bar0_error_status_r(void)
 {
 	return 0x0010a7b0U;
 }
+static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
+{
+	return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
+{
+	return U32(0x1U) << 1U;
+}
+static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
+{
+	return U32(0x1U) << 2U;
+}
+static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
+{
+	return U32(0x1U) << 3U;
+}
+static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
+{
+	return U32(0x1U) << 30U;
+}
+static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
+{
+	return U32(0x1U) << 31U;
+}
 static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
 {
 	return 0x0010a6c0U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
index 47f11aae9..642ea6efb 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -814,10 +814,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
 {
 	return 0x0010a988U;
 }
+static inline u32 pwr_pmu_bar0_host_error_r(void)
+{
+	return 0x0010a990U;
+}
 static inline u32 pwr_pmu_bar0_error_status_r(void)
 {
 	return 0x0010a7b0U;
 }
+static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
+{
+	return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
+{
+	return U32(0x1U) << 1U;
+}
+static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
+{
+	return U32(0x1U) << 2U;
+}
+static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
+{
+	return U32(0x1U) << 3U;
+}
+static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
+{
+	return U32(0x1U) << 30U;
+}
+static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
+{
+	return U32(0x1U) << 31U;
+}
 static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
 {
 	return 0x0010a6c0U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
index 84d815e86..2d7ec825a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -822,10 +822,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
 {
 	return 0x0010a988U;
 }
+static inline u32 pwr_pmu_bar0_host_error_r(void)
+{
+	return 0x0010a990U;
+}
 static inline u32 pwr_pmu_bar0_error_status_r(void)
 {
 	return 0x0010a7b0U;
 }
+static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
+{
+	return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
+{
+	return U32(0x1U) << 1U;
+}
+static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
+{
+	return U32(0x1U) << 2U;
+}
+static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
+{
+	return U32(0x1U) << 3U;
+}
+static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
+{
+	return U32(0x1U) << 30U;
+}
+static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
+{
+	return U32(0x1U) << 31U;
+}
 static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
 {
 	return 0x0010a6c0U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
index 8d3ef82d3..d304a8dd5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -818,10 +818,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
 {
 	return 0x0010a988U;
 }
+static inline u32 pwr_pmu_bar0_host_error_r(void)
+{
+	return 0x0010a990U;
+}
 static inline u32 pwr_pmu_bar0_error_status_r(void)
 {
 	return 0x0010a7b0U;
 }
+static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
+{
+	return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
+{
+	return U32(0x1U) << 1U;
+}
+static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
+{
+	return U32(0x1U) << 2U;
+}
+static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
+{
+	return U32(0x1U) << 3U;
+}
+static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
+{
+	return U32(0x1U) << 30U;
+}
+static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
+{
+	return U32(0x1U) << 31U;
+}
 static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
 {
 	return 0x0010a6c0U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
index b667f0eb5..a593495c2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -922,10 +922,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
 {
 	return 0x0010a988U;
 }
+static inline u32 pwr_pmu_bar0_host_error_r(void)
+{
+	return 0x0010a990U;
+}
 static inline u32 pwr_pmu_bar0_error_status_r(void)
 {
 	return 0x0010a7b0U;
 }
+static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
+{
+	return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
+{
+	return U32(0x1U) << 1U;
+}
+static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
+{
+	return U32(0x1U) << 2U;
+}
+static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
+{
+	return U32(0x1U) << 3U;
+}
+static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
+{
+	return U32(0x1U) << 30U;
+}
+static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
+{
+	return U32(0x1U) << 31U;
+}
 static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
 {
 	return 0x0010a6c0U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
index 4e8bbbb88..30ac53ea8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -978,10 +978,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
 {
 	return 0x0010a988U;
 }
+static inline u32 pwr_pmu_bar0_host_error_r(void)
+{
+	return 0x0010a990U;
+}
 static inline u32 pwr_pmu_bar0_error_status_r(void)
 {
 	return 0x0010a7b0U;
 }
+static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
+{
+	return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
+{
+	return U32(0x1U) << 1U;
+}
+static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
+{
+	return U32(0x1U) << 2U;
+}
+static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
+{
+	return U32(0x1U) << 3U;
+}
+static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
+{
+	return U32(0x1U) << 30U;
+}
+static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
+{
+	return U32(0x1U) << 31U;
+}
 static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
 {
 	return 0x0010a6c0U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h
index 2c4c0750e..e3cd798fc 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -922,10 +922,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
 {
 	return 0x0010a988U;
 }
+static inline u32 pwr_pmu_bar0_host_error_r(void)
+{
+	return 0x0010a990U;
+}
 static inline u32 pwr_pmu_bar0_error_status_r(void)
 {
 	return 0x0010a7b0U;
 }
+static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
+{
+	return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
+{
+	return U32(0x1U) << 1U;
+}
+static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
+{
+	return U32(0x1U) << 2U;
+}
+static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
+{
+	return U32(0x1U) << 3U;
+}
+static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
+{
+	return U32(0x1U) << 30U;
+}
+static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
+{
+	return U32(0x1U) << 31U;
+}
 static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
 {
 	return 0x0010a6c0U + i*4U;