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gpu: nvgpu: add gr manager and mig infra

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This CL covers the code changes related to following support,
 - Added gr manager infra.
 - Added grmgr_gops infra.
 - Added mig infra.
 - Added log mask for MIG verbose support.

JIRA NVGPU-5645
JIRA NVGPU-5646

Change-Id: Iec356e08e6cfee86ad9f59fdf6cfee9c38231359
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2385111
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Lakshmanan M
2020-07-24 12:01:59 +05:30
committed by Alex Waterman
parent 969b901999
commit c99afa1766
15 changed files with 457 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/nvgpu-common.yaml
View File

@@ -1008,6 +1008,14 @@ swdebug:
include/nvgpu/swprofile.h,
include/nvgpu/fifo/swprofile.h ]
grmgr:
owner: Lakshmanan M
safe: no
sources: [ common/grmgr/grmgr.c,
include/nvgpu/grmgr.h,
include/nvgpu/mig.h,
include/nvgpu/gops_grmgr.h ]
##
## HAL units. Currently they are under common but this needs to change.
## We are moving these to a top level directory.

1
drivers/gpu/nvgpu/Makefile
View File

@@ -292,6 +292,7 @@ nvgpu-y += \
common/clk_arb/clk_arb.o \
common/clk_arb/clk_arb_gp10b.o \
common/rc/rc.o \
common/grmgr/grmgr.o \
hal/bus/bus_gk20a.o \
hal/class/class_gm20b.o \
hal/class/class_gp10b.o \

1
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -150,6 +150,7 @@ srcs += common/device.c \
common/mc/mc.c \
common/rc/rc.c \
common/ce/ce.c \
common/grmgr/grmgr.c \
hal/init/hal_gv11b.c \
hal/init/hal_gv11b_litter.c \
hal/init/hal_init.c \

143
drivers/gpu/nvgpu/common/grmgr/grmgr.c Normal file
View File

@@ -0,0 +1,143 @@
/*
* GR MANAGER
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/enabled.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/grmgr.h>
#include <nvgpu/engines.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/gr_utils.h>
int nvgpu_init_gr_manager(struct gk20a *g)
{
struct nvgpu_gpu_instance *gpu_instance = &g->mig.gpu_instance[0];
struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe;
struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
/* Number of gpu instance is 1 for legacy mode */
g->mig.num_gpu_instances = 1U;
g->mig.current_gpu_instance_config_id = 0U;
g->mig.is_nongr_engine_sharable = false;
gpu_instance->gpu_instance_id = 0U;
gpu_instance->is_memory_partition_supported = false;
gr_syspipe->gr_instance_id = 0U;
gr_syspipe->gr_syspipe_id = 0U;
gr_syspipe->engine_id = 0U;
gr_syspipe->num_gpc = nvgpu_gr_config_get_gpc_count(gr_config);
g->mig.gpcgrp_gpc_count[0] = gr_syspipe->num_gpc;
gr_syspipe->logical_gpc_mask = nvgpu_gr_config_get_gpc_mask(gr_config);
/* In Legacy mode, Local GPC Id = physical GPC Id = Logical GPC Id */
gr_syspipe->gpc_mask = gr_syspipe->logical_gpc_mask;
gr_syspipe->physical_gpc_mask = gr_syspipe->gpc_mask;
gr_syspipe->max_veid_count_per_tsg = g->fifo.max_subctx_count;
gr_syspipe->veid_start_offset = 0U;
gpu_instance->num_lce = nvgpu_engine_get_ids(g,
gpu_instance->lce_engine_ids,
NVGPU_MIG_MAX_ENGINES, NVGPU_ENGINE_ASYNC_CE);
if (gpu_instance->num_lce == 0U) {
nvgpu_err(g, "nvgpu_init_gr_manager[failed]-no LCEs");
return -ENOMEM;
}
g->mig.max_gr_sys_pipes_supported = 1U;
g->mig.gr_syspipe_en_mask = 1U;
g->mig.num_gr_sys_pipes_enabled = 1U;
g->mig.current_gr_syspipe_id = NVGPU_MIG_INVALID_GR_SYSPIPE_ID;
nvgpu_log(g, gpu_dbg_mig,
"[non MIG boot] gpu_instance_id[%u] gr_instance_id[%u] "
"gr_syspipe_id[%u] num_gpc[%u] physical_gpc_mask[%x] "
"logical_gpc_mask[%x] gr_engine_id[%u] "
"max_veid_count_per_tsg[%u] veid_start_offset[%u] "
"veid_end_offset[%u] gpcgrp_id[%u] "
"is_memory_partition_support[%d] num_lce[%u] ",
gpu_instance->gpu_instance_id,
gr_syspipe->gr_instance_id,
gr_syspipe->gr_syspipe_id,
gr_syspipe->num_gpc,
gr_syspipe->physical_gpc_mask,
gr_syspipe->logical_gpc_mask,
gr_syspipe->engine_id,
gr_syspipe->max_veid_count_per_tsg,
gr_syspipe->veid_start_offset,
nvgpu_safe_sub_u32(
nvgpu_safe_add_u32(gr_syspipe->veid_start_offset,
gr_syspipe->max_veid_count_per_tsg), 1U),
gr_syspipe->gpcgrp_id,
gpu_instance->is_memory_partition_supported,
gpu_instance->num_lce);
return 0;
}
int nvgpu_grmgr_config_gr_remap_window(struct gk20a *g,
u32 gr_syspipe_id, bool enable)
{
int err = 0;
#if defined(CONFIG_NVGPU_NEXT) && defined(CONFIG_NVGPU_MIG)
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
/*
* GR remap window enable/disable sequence:
* 1) Config_gr_remap_window (syspipe_index, enable).
* 2) Acquire gr_syspipe_lock.
* 3) HW write to enable the gr syspipe programming.
* 4) Return success.
* 5) Do GR programming belong to particular gr syspipe.
* 6) Config_gr_remap_window (syspipe_index, disable).
* 7) HW write to disable the gr syspipe programming.
* 8) Release the gr_syspipe_lock.
*/
if (enable) {
nvgpu_mutex_acquire(&g->mig.gr_syspipe_lock);
} else {
gr_syspipe_id = 0U;
}
if (((g->mig.current_gr_syspipe_id != gr_syspipe_id) &&
(gr_syspipe_id <
g->ops.grmgr.get_max_sys_pipes(g))) ||
(enable == false)) {
err = g->ops.priv_ring.config_gr_remap_window(g,
gr_syspipe_id, enable);
}
if (err == 0) {
if (enable) {
g->mig.current_gr_syspipe_id = gr_syspipe_id;
} else {
g->mig.current_gr_syspipe_id =
NVGPU_MIG_INVALID_GR_SYSPIPE_ID;
nvgpu_mutex_release(&g->mig.gr_syspipe_lock);
}
}
}
#endif
return err;
}

4
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -55,6 +55,7 @@
#include <nvgpu/fbp.h>
#include <nvgpu/therm.h>
#include <nvgpu/clk_arb.h>
#include <nvgpu/grmgr.h>
#include "hal/mm/mm_gk20a.h"
#include "hal/mm/mm_gm20b.h"
@@ -1125,6 +1126,9 @@ static const struct gpu_ops gm20b_ops = {
.tpc_gr_pg = NULL,
},
#endif
.grmgr = {
.init_gr_manager = nvgpu_init_gr_manager,
},
.chip_init_gpu_characteristics = nvgpu_init_gpu_characteristics,
.get_litter_value = gm20b_get_litter_value,
};

4
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -55,6 +55,7 @@
#include <nvgpu/fbp.h>
#include <nvgpu/therm.h>
#include <nvgpu/clk_arb.h>
#include <nvgpu/grmgr.h>
#include "hal/mm/mm_gk20a.h"
#include "hal/mm/mm_gm20b.h"
@@ -1239,6 +1240,9 @@ static const struct gpu_ops gp10b_ops = {
.tpc_gr_pg = NULL,
},
#endif
.grmgr = {
.init_gr_manager = nvgpu_init_gr_manager,
},
.chip_init_gpu_characteristics = gp10b_init_gpu_characteristics,
.get_litter_value = gp10b_get_litter_value,
};

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -204,6 +204,7 @@
#include <nvgpu/gr/fecs_trace.h>
#include <nvgpu/gr/gr_intr.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/grmgr.h>
#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
@@ -1502,6 +1503,9 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
.tpc_gr_pg = gv11b_gr_pg_tpc,
},
#endif
.grmgr = {
.init_gr_manager = nvgpu_init_gr_manager,
},
.chip_init_gpu_characteristics = gv11b_init_gpu_characteristics,
.get_litter_value = gv11b_get_litter_value,
};

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -243,6 +243,7 @@
#include <nvgpu/nvhost.h>
#include <nvgpu/nvlink.h>
#include <nvgpu/clk_mon.h>
#include <nvgpu/grmgr.h>
#include <nvgpu/hw/tu104/hw_pwr_tu104.h>
@@ -1634,6 +1635,9 @@ static const struct gpu_ops tu104_ops = {
.get_num_ltcs = gm20b_top_get_num_ltcs,
.get_num_lce = gv11b_top_get_num_lce,
},
.grmgr = {
.init_gr_manager = nvgpu_init_gr_manager,
},
.chip_init_gpu_characteristics = tu104_init_gpu_characteristics,
.get_litter_value = tu104_get_litter_value,
};

4
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
View File

@@ -38,6 +38,7 @@
#include <nvgpu/fbp.h>
#include <nvgpu/therm.h>
#include <nvgpu/clk_arb.h>
#include <nvgpu/grmgr.h>
#include <nvgpu/vgpu/ce_vgpu.h>
#include <nvgpu/vgpu/vm_vgpu.h>
@@ -857,6 +858,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
.parse_next_device = vgpu_top_parse_next_dev,
},
.grmgr = {
.init_gr_manager = nvgpu_init_gr_manager,
},
.chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
.get_litter_value = gp10b_get_litter_value,
};

4
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
View File

@@ -108,6 +108,7 @@
#include <nvgpu/fbp.h>
#include <nvgpu/therm.h>
#include <nvgpu/clk_arb.h>
#include <nvgpu/grmgr.h>
#include "common/vgpu/init/init_vgpu.h"
#include "common/vgpu/fb/fb_vgpu.h"
@@ -982,6 +983,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
.parse_next_device = vgpu_top_parse_next_dev,
},
.grmgr = {
.init_gr_manager = nvgpu_init_gr_manager,
},
.chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics,
.get_litter_value = gv11b_get_litter_value,
};

11
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -140,6 +140,7 @@ enum nvgpu_profiler_pm_reservation_scope;
#include <nvgpu/semaphore.h>
#include <nvgpu/fifo.h>
#include <nvgpu/sched.h>
#include <nvgpu/mig.h>
#include <nvgpu/gops_class.h>
#include <nvgpu/gops_ce.h>
@@ -170,13 +171,10 @@ enum nvgpu_profiler_pm_reservation_scope;
#include <nvgpu/gops_cg.h>
#include <nvgpu/gops_pmu.h>
#include <nvgpu/gops_ecc.h>
#include <nvgpu/gops_grmgr.h>
#include "hal/clk/clk_gk20a.h"
#if defined(CONFIG_NVGPU_NEXT) && defined(CONFIG_NVGPU_MIG)
#include "include/nvgpu/nvgpu_next_gops_grmgr.h"
#endif
#ifdef CONFIG_DEBUG_FS
struct railgate_stats {
unsigned long last_rail_gate_start;
@@ -646,9 +644,7 @@ struct gpu_ops {
#endif
void (*semaphore_wakeup)(struct gk20a *g, bool post_events);
#if defined(CONFIG_NVGPU_NEXT) && defined(CONFIG_NVGPU_MIG)
struct gops_grmgr grmgr;
#endif
};
@@ -1042,6 +1038,9 @@ struct gk20a {
/** Max SM diversity configuration count. */
u32 max_sm_diversity_config_count;
/** Multi Instance GPU information. */
struct nvgpu_mig mig;
};
/**

64
drivers/gpu/nvgpu/include/nvgpu/gops_grmgr.h Normal file
View File

@@ -0,0 +1,64 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_GOPS_GRMGR_H
#define NVGPU_GOPS_GRMGR_H
#include <nvgpu/types.h>
/**
* @file
*
* GR MANAGER unit HAL interface
*
*/
struct gk20a;
/**
* GR MANAGER unit HAL operations
*
* @see gpu_ops
*/
struct gops_grmgr {
/**
* @brief Initialize GR Manager unit.
*
* @param g [in] Pointer to GPU driver struct.
*
* @return 0 in case of success, < 0 in case of failure.
*/
int (*init_gr_manager)(struct gk20a *g);
/**
* @brief Remove GR Manager unit.
*
* @param g [in] Pointer to GPU driver struct.
*
* @return 0 in case of success, < 0 in case of failure.
*/
int (*remove_gr_manager)(struct gk20a *g);
#if defined(CONFIG_NVGPU_NEXT) && defined(CONFIG_NVGPU_MIG)
#include "include/nvgpu/nvgpu_next_gops_grmgr.h"
#endif
};
#endif /* NVGPU_NEXT_GOPS_GRMGR_H */

37
drivers/gpu/nvgpu/include/nvgpu/grmgr.h Normal file
View File

@@ -0,0 +1,37 @@
/*
* GR MANAGER
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_GRMGR_H
#define NVGPU_GRMGR_H
#include <nvgpu/types.h>
struct gk20a;
int nvgpu_init_gr_manager(struct gk20a *g);
int nvgpu_grmgr_config_gr_remap_window(struct gk20a *g,
u32 gr_syspipe_id, bool enable);
#endif /* NVGPU_GRMGR_H */

3
drivers/gpu/nvgpu/include/nvgpu/log_common.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -70,5 +70,6 @@ enum nvgpu_log_type {
#define gpu_dbg_mem BIT(31) /* memory accesses; very verbose. */
#define gpu_dbg_device BIT(32) /* Device initialization and
querying. */
#define gpu_dbg_mig BIT(33) /* MIG info */
#endif

172
drivers/gpu/nvgpu/include/nvgpu/mig.h Normal file
View File

@@ -0,0 +1,172 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_MIG_H
#define NVGPU_MIG_H
#include <nvgpu/types.h>
#include <nvgpu/lock.h>
/** Maximum GPC group supported by HW. */
#define NVGPU_MIG_MAX_GPCGRP 2U
/** Maximum gpu instances count. */
#define NVGPU_MIG_MAX_GPU_INSTANCES 8U
/** Maximum mig config count. */
#define NVGPU_MIG_MAX_MIG_CONFIG_COUNT 16U
/** INVALID sys pipe id. */
#define NVGPU_MIG_INVALID_GR_SYSPIPE_ID (~U32(0U))
/** Maximum engine slot count. */
#define NVGPU_MIG_MAX_ENGINES 32U
/** Maximum config name size. */
#define NVGPU_MIG_MAX_CONFIG_NAME_SIZE 256U
/**
* @brief GR syspipe information.
* This struct describes the number of gpc, physical_gpc_mask, veid, etc
* associated to a particualr gr syspipe.
*/
struct nvgpu_gr_syspipe {
/** GR sys pipe instance Id */
u32 gr_instance_id;
/** GR syspipe id which is used to set gr remap window */
u32 gr_syspipe_id;
/**
* The unique per-device ID that host uses to identify any given engine.
*/
u32 engine_id;
/** Number of GPC assigned to this gr syspipe. */
u32 num_gpc;
/**
* Mask of Physical GPCs. A set bit indicates GPC is available,
* otherwise it is not available.
*/
u32 physical_gpc_mask;
/**
* Mask of Logical GPCs. A set bit indicates GPC is available,
* otherwise it is not available.
*/
u32 logical_gpc_mask;
/**
* Mask of local GPCs belongs to this syspipe. A set bit indicates
* GPC is available, otherwise it is not available.
*/
u32 gpc_mask;
/** Maximum veid allocated to this gr syspipe. */
u32 max_veid_count_per_tsg;
/** VEID start offset. */
u32 veid_start_offset;
/** GPC group Id. */
u32 gpcgrp_id;
};
/**
* @brief GPU instance information.
* This struct describes the gr_syspipe, LCEs, etc associated
* to a particualr gpu instance.
*/
struct nvgpu_gpu_instance {
/** GPU instance Id */
u32 gpu_instance_id;
/** GR syspipe information. */
struct nvgpu_gr_syspipe gr_syspipe;
/** Number of Logical CE engine associated to this gpu instances. */
u32 num_lce;
/** Memory area to store h/w CE engine ids. */
u32 lce_engine_ids[NVGPU_MIG_MAX_ENGINES];
/* Flag to indicate whether memory partition is supported or not. */
bool is_memory_partition_supported;
};
/**
* @brief GPU instance configuration information.
* This struct describes the number of gpu instances, gr_syspipe, LCEs, etc
* associated to a particualr mig config.
*/
struct nvgpu_gpu_instance_config {
/** Name of the gpu instance config. */
const char config_name[NVGPU_MIG_MAX_CONFIG_NAME_SIZE];
/** Number of gpu instance associated to this config. */
u32 num_gpu_instances;
/** Array of gpu instance information associated to this config. */
struct nvgpu_gpu_instance
gpu_instance[NVGPU_MIG_MAX_GPU_INSTANCES];
};
/**
* @brief MIG configuration options.
* This struct describes the various number of mig gpu instance configuration
* supported by a particual GPU.
*/
struct nvgpu_mig_gpu_instance_config {
/** Number of gpu instance configurations. */
u32 num_config_supported;
/** GPC count associated to each GPC group. */
u32 gpcgrp_gpc_count[NVGPU_MIG_MAX_GPCGRP];
/** Array of gpu instance configuration information. */
struct nvgpu_gpu_instance_config
gpu_instance_config[NVGPU_MIG_MAX_MIG_CONFIG_COUNT];
};
/**
* @brief Multi Instance GPU information.
* This struct describes the mig top level information supported
* by a particual GPU.
*/
struct nvgpu_mig {
/** GPC count associated to each GPC group. */
u32 gpcgrp_gpc_count[NVGPU_MIG_MAX_GPCGRP];
/** Enabled gpu instances count. */
u32 num_gpu_instances;
/** Maximum gr sys pipes are supported by HW. */
u32 max_gr_sys_pipes_supported;
/** Total number of enabled gr syspipes count. */
u32 num_gr_sys_pipes_enabled;
/** GR sys pipe enabled mask. */
u32 gr_syspipe_en_mask;
/**
* Current gr syspipe id.
* It is valid if num_gr_sys_pipes_enabled > 1.
*/
u32 current_gr_syspipe_id;
/**
* GR syspipe acquire lock.
* It is valid lock if num_gr_sys_pipes_enabled > 1.
*/
struct nvgpu_mutex gr_syspipe_lock;
/** Gpu instance configuration id. */
u32 current_gpu_instance_config_id;
/**
* Flag to indicate whether nonGR(CE) engine is sharable
* between gr syspipes or not.
*/
bool is_nongr_engine_sharable;
/** Array of enabled gpu instance information. */
struct nvgpu_gpu_instance
gpu_instance[NVGPU_MIG_MAX_GPU_INSTANCES];
};
#endif /* NVGPU_MIG_H */