From c9cb1aab1cbbb929bf1889a7a73e8a6d7ccf33f7 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Thu, 28 Mar 2019 10:16:26 +0530 Subject: [PATCH] gpu: nvgpu: remove uneeded seq_desc, msg parameter of sec2_cmd_post and callback These parameters are not required. Removing those will simplify the refactoring of the IPC units. The plan is to keep access to sequence struct members within IPC units. JIRA NVGPU-2075 Change-Id: Idf62082152448230d286cfc5e7249c9886d8251a Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2085747 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/sec2/sec2.c | 7 +++---- drivers/gpu/nvgpu/common/sec2/sec2_ipc.c | 16 ++++------------ drivers/gpu/nvgpu/include/nvgpu/sec2.h | 11 +++-------- 3 files changed, 10 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nvgpu/common/sec2/sec2.c b/drivers/gpu/nvgpu/common/sec2/sec2.c index cba87a7aa..a1d894b79 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2.c @@ -136,7 +136,7 @@ int nvgpu_sec2_destroy(struct gk20a *g) /* LSF's bootstrap command */ static void sec2_handle_lsfm_boot_acr_msg(struct gk20a *g, struct nv_flcn_msg_sec2 *msg, - void *param, u32 handle, u32 status) + void *param, u32 status) { bool *command_ack = param; @@ -156,7 +156,6 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, { struct nv_flcn_cmd_sec2 cmd; bool command_ack; - u32 seq = 0; int err = 0; size_t tmp_size; @@ -179,8 +178,8 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, falcon_id); command_ack = false; - err = nvgpu_sec2_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_HPQ, - sec2_handle_lsfm_boot_acr_msg, &command_ack, &seq, U32_MAX); + err = nvgpu_sec2_cmd_post(g, &cmd, PMU_COMMAND_QUEUE_HPQ, + sec2_handle_lsfm_boot_acr_msg, &command_ack, U32_MAX); if (err != 0) { nvgpu_err(g, "command post failed"); } diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c b/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c index 68eb44543..cff36f0be 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c @@ -71,10 +71,8 @@ static void sec2_seq_release(struct nvgpu_sec2 *sec2, struct sec2_sequence *seq) { seq->state = SEC2_SEQ_STATE_FREE; - seq->desc = SEC2_INVALID_SEQ_DESC; seq->callback = NULL; seq->cb_params = NULL; - seq->msg = NULL; seq->out_payload = NULL; clear_bit((int)seq->id, sec2->sec2_seq_tbl); @@ -145,18 +143,16 @@ static int sec2_write_cmd(struct nvgpu_sec2 *sec2, } int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd, - struct nv_flcn_msg_sec2 *msg, u32 queue_id, sec2_callback callback, - void *cb_param, u32 *seq_desc, u32 timeout) + u32 queue_id, sec2_callback callback, + void *cb_param, u32 timeout) { struct nvgpu_sec2 *sec2 = &g->sec2; struct sec2_sequence *seq = NULL; int err = 0; - if ((cmd == NULL) || (seq_desc == NULL) || (!sec2->sec2_ready)) { + if ((cmd == NULL) || (!sec2->sec2_ready)) { if (cmd == NULL) { nvgpu_warn(g, "%s(): SEC2 cmd buffer is NULL", __func__); - } else if (seq_desc == NULL) { - nvgpu_warn(g, "%s(): Seq descriptor is NULL", __func__); } else { nvgpu_warn(g, "%s(): SEC2 is not ready", __func__); } @@ -185,11 +181,7 @@ int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd, seq->callback = callback; seq->cb_params = cb_param; - seq->msg = msg; seq->out_payload = NULL; - seq->desc = sec2->next_seq_desc++; - - *seq_desc = seq->desc; seq->state = SEC2_SEQ_STATE_USED; @@ -220,7 +212,7 @@ static int sec2_response_handle(struct nvgpu_sec2 *sec2, } if (seq->callback != NULL) { - seq->callback(g, msg, seq->cb_params, seq->desc, ret); + seq->callback(g, msg, seq->cb_params, ret); } /* release the sequence so that it may be used for other commands */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2.h b/drivers/gpu/nvgpu/include/nvgpu/sec2.h index 83287608a..e21b08ea0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2.h @@ -45,8 +45,6 @@ #define SEC2_SEQ_TBL_SIZE \ (SEC2_MAX_NUM_SEQUENCES >> SEC2_SEQ_BIT_SHIFT) -#define SEC2_INVALID_SEQ_DESC (~0U) - enum sec2_seq_state { SEC2_SEQ_STATE_FREE = 0U, SEC2_SEQ_STATE_PENDING, @@ -55,13 +53,11 @@ enum sec2_seq_state { }; typedef void (*sec2_callback)(struct gk20a *g, struct nv_flcn_msg_sec2 *msg, - void *param, u32 handle, u32 status); + void *param, u32 status); struct sec2_sequence { u8 id; enum sec2_seq_state state; - u32 desc; - struct nv_flcn_msg_sec2 *msg; u8 *out_payload; sec2_callback callback; void *cb_params; @@ -76,7 +72,6 @@ struct nvgpu_sec2 { struct sec2_sequence *seq; unsigned long sec2_seq_tbl[SEC2_SEQ_TBL_SIZE]; - u32 next_seq_desc; struct nvgpu_mutex sec2_seq_lock; bool isr_enabled; @@ -96,8 +91,8 @@ struct nvgpu_sec2 { /* command/message handling methods*/ int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd, - struct nv_flcn_msg_sec2 *msg, u32 queue_id, sec2_callback callback, - void *cb_param, u32 *seq_desc, u32 timeout); + u32 queue_id, sec2_callback callback, + void *cb_param, u32 timeout); int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2); int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms, void *var, u8 val);