diff --git a/drivers/gpu/nvgpu/common/grmgr/grmgr.c b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
index 1ca9d37d1..a16abe573 100644
--- a/drivers/gpu/nvgpu/common/grmgr/grmgr.c
+++ b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
@@ -42,11 +42,9 @@ int nvgpu_init_gr_manager(struct gk20a *g)
 	int err = 0;
 	const struct nvgpu_device *gr_dev = NULL;
 
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
 	if (g->ops.grmgr.load_timestamp_prod != NULL) {
 		g->ops.grmgr.load_timestamp_prod(g);
 	}
-#endif
 	/* Number of gpu instance is 1 for legacy mode */
 	g->mig.max_gpc_count = g->ops.top.get_max_gpc_count(g);
 	nvgpu_assert(g->mig.max_gpc_count > 0U);
diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
index 747566589..32870e2d0 100644
--- a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
@@ -955,7 +955,6 @@ int ga10b_grmgr_get_mig_gpu_instance_config(struct gk20a *g,
 
 #endif
 
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
 void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g)
 {
 	u32 reg_val;
@@ -968,7 +967,6 @@ void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g)
 	nvgpu_writel(g, smcarb_timestamp_ctrl_r(), reg_val);
 
 }
-#endif
 
 int ga10b_grmgr_discover_gpc_ids(struct gk20a *g,
 		u32 num_gpc, struct nvgpu_gpc *gpcs)
diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h
index dc97c6c1f..7694954b8 100644
--- a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h
@@ -42,9 +42,7 @@ int ga10b_grmgr_get_mig_gpu_instance_config(struct gk20a *g,
 void ga10b_grmgr_get_gpcgrp_count(struct gk20a *g);
 #endif
 
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
 void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g);
-#endif
 int ga10b_grmgr_discover_gpc_ids(struct gk20a *g,
 		u32 num_gpc, struct nvgpu_gpc *gpcs);
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
index 612385b04..c08b55bbe 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -1728,9 +1728,7 @@ static const struct gops_grmgr ga100_ops_grmgr = {
 #else
 	.init_gr_manager = nvgpu_init_gr_manager,
 #endif
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
 	.load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod,
-#endif
 	.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,
 };
 #endif
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index c24e55152..4dc0d21e3 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -1707,9 +1707,7 @@ static const struct gops_grmgr ga10b_ops_grmgr = {
 #else
 	.init_gr_manager = nvgpu_init_gr_manager,
 #endif
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
 	.load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod,
-#endif
 	.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,
 };
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h
index aa74ba7bf..f1aacdaf2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -85,8 +85,8 @@ struct gops_grmgr {
 			u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id);
 	int (*get_mig_gpu_instance_config)(struct gk20a *g,
 		const char **config_name, u32 *num_config_supported);
-	void (*load_timestamp_prod)(struct gk20a *g);
 #endif
+	void (*load_timestamp_prod)(struct gk20a *g);
 };
 
 #endif /* NVGPU_GOPS_GRMGR_H */