From ca636eaeb73b4a9f48d4dfd6a973a6bc09200ac7 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 16 Feb 2021 19:41:33 -0800 Subject: [PATCH] gpu: nvgpu: gops: mc: add doxygen for ltc_isr Add doxygen for mc.ltc_isr, since it is getting called from fusa code. Jira NVGPU-6182 Change-Id: I1995cb6a2caef11f0b982b76b5dcd8d809d78a44 Signed-off-by: Seshendra Gadagottu (cherry picked from commit 8ddc5e9dbbe7d711baafe1e824111010fcc969fb) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488417 GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions Reviewed-by: Alex Waterman Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/gops/mc.h | 34 +++++++++++------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h index 53db3f957..dfae6235b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h @@ -200,7 +200,22 @@ struct gops_mc { bool (*is_stall_and_eng_intr_pending)(struct gk20a *g, u32 engine_id, u32 *eng_intr_pending); - + /** + * @brief Interrupt Service Routine (ISR) for handling the Level Two + * Cache (LTC) interrupts. + * + * @param g [in] The GPU driver struct. + * + * This function is invoked to handle the LTC interrupts from + * #isr_stall. + * + * Steps: + * - Read mc_intr_ltc_r register to get the interrupts status for LTCs. + * - For each ltc from index 0 to nvgpu_ltc_get_ltc_count(\a g) + * - If interrupt bitmask is set in the interrupts status register + * - Invoke g->ops.ltc.intr.isr. + */ + void (*ltc_isr)(struct gk20a *g); /** @cond DOXYGEN_SHOULD_SKIP_THIS */ @@ -252,23 +267,6 @@ struct gops_mc { void (*fbpa_isr)(struct gk20a *g); #endif - /** - * @brief Interrupt Service Routine (ISR) for handling the Level Two - * Cache (LTC) interrupts. - * - * @param g [in] The GPU driver struct. - * - * This function is invoked to handle the LTC interrupts from - * #isr_stall. - * - * Steps: - * - Read mc_intr_ltc_r register to get the interrupts status for LTCs. - * - For each ltc from index 0 to nvgpu_ltc_get_ltc_count(\a g) - * - If interrupt bitmask is set in the interrupts status register - * - Invoke g->ops.ltc.intr.isr. - */ - void (*ltc_isr)(struct gk20a *g); - #if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT) #include "include/nvgpu/nvgpu_next_gops_mc.h" #endif