From cae88e7451a9d7118efa2e2b98680dd39838db37 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 17 Dec 2020 22:25:45 +0530 Subject: [PATCH] gpu: nvgpu: initialize cau data while binding HWPM in global mode Add CAU initialization data in const array hwpm_cau_init_data[]. Add HAL API gops.gr.get_hwpm_cau_init_data() to retrieve this data and implement it for TU104. Add new HAL API gops.gr.init_cau() that uses above data and initializes all cau units. Implement this HAL only for TU104. Invoke above sequence from nvgpu_profiler_bind_hwpm() in case of global HWPM mode. Jira NVGPU-5360 Change-Id: I1c7a380e9d04d6cd45fb7f746c0a79fc56675244 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2463854 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/profiler/profiler.c | 3 ++ drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c | 51 ++++++++++++++++++++ drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.h | 2 + drivers/gpu/nvgpu/hal/init/hal_tu104.c | 2 + drivers/gpu/nvgpu/include/nvgpu/gops/gr.h | 2 + 5 files changed, 60 insertions(+) diff --git a/drivers/gpu/nvgpu/common/profiler/profiler.c b/drivers/gpu/nvgpu/common/profiler/profiler.c index 2248102f9..e50c17326 100644 --- a/drivers/gpu/nvgpu/common/profiler/profiler.c +++ b/drivers/gpu/nvgpu/common/profiler/profiler.c @@ -351,6 +351,9 @@ static int nvgpu_profiler_bind_hwpm(struct nvgpu_profiler_object *prof, bool str if (prof->ctxsw[NVGPU_PROFILER_PM_RESOURCE_TYPE_HWPM_LEGACY]) { err = g->ops.gr.update_hwpm_ctxsw_mode(g, prof->tsg, 0, mode); } else { + if (g->ops.gr.init_cau != NULL) { + g->ops.gr.init_cau(g); + } if (g->ops.perf.reset_hwpm_pmm_registers != NULL) { g->ops.perf.reset_hwpm_pmm_registers(g); } diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c index 773f2260d..83351a466 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c @@ -151,3 +151,54 @@ void tu104_gr_disable_smpc(struct gk20a *g) g->ops.priv_ring.read_pri_fence(g); } } + +static const u32 hwpm_cau_init_data[] = +{ + /* This list is autogenerated. Do not edit. */ + 0x00419980, + 0x00000000, + 0x00419988, + 0x00000000, + 0x0041998c, + 0x00000000, + 0x00419990, + 0x00000000, + 0x00419994, + 0x00000000, + 0x00419998, + 0x00000000, + 0x0041999c, + 0x00000000, + 0x004199a4, + 0x00000001, +}; + +const u32 *tu104_gr_get_hwpm_cau_init_data(u32 *count) +{ + *count = sizeof(hwpm_cau_init_data) / sizeof(hwpm_cau_init_data[0]); + return hwpm_cau_init_data; +} + +void tu104_gr_init_cau(struct gk20a *g) +{ + const u32 *data; + u32 cau_stride; + u32 num_cau; + u32 count; + u32 i, j; + + num_cau = gr_gpcs_tpcs_cau_control__size_1_v(); + cau_stride = gr_gpcs_tpcs_cau_control_r(1) - gr_gpcs_tpcs_cau_control_r(0); + + data = g->ops.gr.get_hwpm_cau_init_data(&count); + + for (i = 0U; i < num_cau; i++) { + for (j = 0U; j < count; j += 2U) { + nvgpu_writel(g, data[j] + i * cau_stride, data[j + 1U]); + } + } + + if (g->ops.priv_ring.read_pri_fence != NULL) { + g->ops.priv_ring.read_pri_fence(g); + } +} diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.h index 181bbe557..72b4529bf 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.h +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.h @@ -43,6 +43,8 @@ int tu104_gr_update_smpc_global_mode(struct gk20a *g, bool enable); void tu104_gr_disable_cau(struct gk20a *g); void tu104_gr_disable_smpc(struct gk20a *g); +const u32 *tu104_gr_get_hwpm_cau_init_data(u32 *count); +void tu104_gr_init_cau(struct gk20a *g); #endif /* CONFIG_NVGPU_DEBUGGER */ #endif /* NVGPU_GR_TU104_H */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 158e5a40b..95d58dd82 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -699,6 +699,8 @@ static const struct gops_gr tu104_ops_gr = { .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, .disable_cau = tu104_gr_disable_cau, .disable_smpc = tu104_gr_disable_smpc, + .get_hwpm_cau_init_data = tu104_gr_get_hwpm_cau_init_data, + .init_cau = tu104_gr_init_cau, .clear_sm_error_state = gv11b_gr_clear_sm_error_state, .suspend_contexts = gr_gp10b_suspend_contexts, .resume_contexts = gr_gk20a_resume_contexts, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h index 9ab37271d..307977e5e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h @@ -1193,6 +1193,8 @@ struct gops_gr { #endif void (*disable_cau)(struct gk20a *g); void (*disable_smpc)(struct gk20a *g); + const u32 *(*get_hwpm_cau_init_data)(u32 *count); + void (*init_cau)(struct gk20a *g); /** @endcond */ /** This structure stores the GR ecc subunit hal pointers. */