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gpu: nvgpu: add support for disabling l3 via DT

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On volta the GPU determines whether to do L3 allocation for a mapping by
checking bit 36 of the physical address. So if a mapping should allocate lines
in the L3 this bit must be set.

However, when the physical addresses for 64GB of RAM uses the 36th bit
resulting in a conflict. Thus, add support for disabling l3 support
for SKUs having 64GB of physical memory.

Bug 3486025

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: Ic540e754274cf1d9e6625493962699d21509e540
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2661548
(cherry picked from commit 46b43d2b24)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2667676
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Brad Griffis <bgriffis@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Debarshi Dutta
2022-01-31 08:13:19 +05:30
committed by Amulya Yarlagadda
parent 2c441a83d4
commit cb09a821d5
4 changed files with 27 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/include/nvgpu/enabled.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -85,7 +85,12 @@ struct gk20a;
#define NVGPU_MM_USE_PHYSICAL_SG 27
/* WAR for gm20b chips. */
#define NVGPU_MM_FORCE_128K_PMU_VM 28
/* SW ERRATA to disable L3 alloc Bit of the physical address.
* Bit number varies between SOCs.
* E.g. 64GB physical RAM support for gv11b requires this SW errata
* to be enabled.
*/
#define NVGPU_DISABLE_L3_SUPPORT 29
/*
* Host flags
*/

11
drivers/gpu/nvgpu/os/linux/driver_common.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -18,6 +18,7 @@
#include <linux/dma-mapping.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/of_platform.h>
#include <uapi/linux/nvgpu.h>
#include <nvgpu/defaults.h>
@@ -241,6 +242,8 @@ int nvgpu_probe(struct gk20a *g,
struct device *dev = dev_from_gk20a(g);
struct gk20a_platform *platform = dev_get_drvdata(dev);
int err = 0;
struct device_node *np = dev->of_node;
bool disable_l3_alloc = false;
nvgpu_init_vars(g);
nvgpu_init_gr_vars(g);
@@ -265,6 +268,12 @@ int nvgpu_probe(struct gk20a *g,
return err;
}
disable_l3_alloc = of_property_read_bool(np, "disable_l3_alloc");
if (disable_l3_alloc) {
nvgpu_log_info(g, "L3 alloc is disabled\n");
__nvgpu_set_enabled(g, NVGPU_DISABLE_L3_SUPPORT, true);
}
nvgpu_init_mm_vars(g);
/* platform probe can defer do user init only if probe succeeds */

4
drivers/gpu/nvgpu/os/linux/vm.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -50,8 +50,10 @@ static u32 nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags)
core_flags |= NVGPU_VM_MAP_IO_COHERENT;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE)
core_flags |= NVGPU_VM_MAP_UNMAPPED_PTE;
if (!nvgpu_is_enabled(g, NVGPU_DISABLE_L3_SUPPORT)) {
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC)
core_flags |= NVGPU_VM_MAP_L3_ALLOC;
}
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL)
core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC)

4
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
View File

@@ -1,7 +1,7 @@
/*
* Virtualized GPU Memory Management
*
* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -177,8 +177,10 @@ u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
p->flags = TEGRA_VGPU_MAP_CACHEABLE;
if (flags & NVGPU_VM_MAP_IO_COHERENT)
p->flags |= TEGRA_VGPU_MAP_IO_COHERENT;
if (!nvgpu_is_enabled(g, NVGPU_DISABLE_L3_SUPPORT)) {
if (flags & NVGPU_VM_MAP_L3_ALLOC)
p->flags |= TEGRA_VGPU_MAP_L3_ALLOC;
}
if (flags & NVGPU_VM_MAP_PLATFORM_ATOMIC) {
p->flags |= TEGRA_VGPU_MAP_PLATFORM_ATOMIC;
}