From cb110723a5453743f50f4af2fdc335ca4d5ec688 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 17 Sep 2019 18:43:13 +0530 Subject: [PATCH] gpu: nvgpu: doxygen for GR private structures [2/2] Add doxygen documentation for private GR structures defined in: gr/gr_config_priv.h gr/gr_falcon_priv.h gr/gr_intr_priv.h gr/gr_priv.h Remove "p_va" field from struct nvgpu_ctxsw_ucode_info since it is unused. Compile out "pm_ctxsw_image_size" with flag CONFIG_NVGPU_DEBUGGER. Compile out "preempt_image_size" with flag CONFIG_NVGPU_GRAPHICS. Replace eUcodeHandshakeInitComplete enum value by macro FALCON_UCODE_HANDSHAKE_INIT_COMPLETE. And remove enum value eUcodeHandshakeMethodFinished since it is unused. Compile "ctxsw_disable_mutex" and "ctxsw_disable_count" in struct nvgpu_gr only if CONFIG_NVGPU_RECOVERY or CONFIG_NVGPU_DEBUGGER is defined Jira NVGPU-4028 Change-Id: Ie8769c1f3f8d313b479b182d3858a6715d49cd4c Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2201373 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr.c | 2 + drivers/gpu/nvgpu/common/gr/gr_config_priv.h | 95 +++++++++- drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h | 166 +++++++++++++----- drivers/gpu/nvgpu/common/gr/gr_intr_priv.h | 131 +++++++++++++- drivers/gpu/nvgpu/common/gr/gr_priv.h | 65 ++++++- .../hal/gr/falcon/gr_falcon_gm20b_fusa.c | 2 +- 6 files changed, 400 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 4cc958a0a..fdfc525f6 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -429,8 +429,10 @@ static int gr_init_setup_sw(struct gk20a *g) gr->g = g; +#if defined(CONFIG_NVGPU_RECOVERY) || defined(CONFIG_NVGPU_DEBUGGER) nvgpu_mutex_init(&gr->ctxsw_disable_mutex); gr->ctxsw_disable_count = 0; +#endif err = nvgpu_gr_obj_ctx_init(g, &gr->golden_image, nvgpu_gr_falcon_get_golden_image_size(g->gr->falcon)); diff --git a/drivers/gpu/nvgpu/common/gr/gr_config_priv.h b/drivers/gpu/nvgpu/common/gr/gr_config_priv.h index 898ea59e3..136af115b 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_config_priv.h +++ b/drivers/gpu/nvgpu/common/gr/gr_config_priv.h @@ -25,39 +25,132 @@ #include +/** + * Max possible PES count per GPC. + */ #define GK20A_GR_MAX_PES_PER_GPC 3U struct gk20a; +/** + * Detailed information of SM indexes in GR engine. + */ struct nvgpu_sm_info { + /** + * Index of GPC for SM. + */ u32 gpc_index; + + /** + * Index of TPC for SM. + */ u32 tpc_index; + + /** + * Index of SM within TPC. + */ u32 sm_index; + + /** + * Global TPC index for SM. + */ u32 global_tpc_index; }; +/** + * GR engine configuration data. + * + * This data is populated during GR initialization and referred across + * GPU driver through public APIs. + */ struct nvgpu_gr_config { + /** + * Pointer to GPU driver struct. + */ struct gk20a *g; + /** + * Max possible number of GPCs in GR engine. + */ u32 max_gpc_count; + /** + * Max possible number of TPCs per GPC in GR engine. + */ u32 max_tpc_per_gpc_count; + /** + * Max possible number of TPCs in GR engine. + */ u32 max_tpc_count; + /** + * Number of GPCs in GR engine. + */ u32 gpc_count; + /** + * Number of TPCs in GR engine. + */ u32 tpc_count; + /** + * Number of PPCs in GR engine. + */ u32 ppc_count; + + /** + * Number of PES per GPC in GR engine. + */ u32 pe_count_per_gpc; + /** + * Number of SMs per TPC in GR engine. + */ u32 sm_count_per_tpc; + /** + * Array to hold number of PPC units per GPC. + * Array is indexed by GPC index. + */ u32 *gpc_ppc_count; + /** + * Array to hold number of TPCs per GPC. + * Array is indexed by GPC index. + */ u32 *gpc_tpc_count; + /** + * 2-D array to hold number of TPCs attached to a PES unit + * in a GPC. + */ u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC]; + /** + * Mask of GPCs. A set bit indicates GPC is available, otherwise + * it is not available. + */ u32 gpc_mask; + + /** + * Array to hold mask of TPCs per GPC. + * Array is indexed by GPC index. + */ u32 *gpc_tpc_mask; + /** + * 2-D array to hold mask of TPCs attached to a PES unit + * in a GPC. + */ u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC]; + /** + * Array to hold skip mask of TPCs per GPC. + * Array is indexed by GPC index. + */ u32 *gpc_skip_mask; + /** + * Number of SMs in GR engine. + */ + u32 no_of_sm; + /** + * Pointer to SM information struct. + */ + struct nvgpu_sm_info *sm_to_cluster; + #ifdef CONFIG_NVGPU_GRAPHICS u32 max_zcull_per_gpc_count; u32 zcb_count; @@ -67,8 +160,6 @@ struct nvgpu_gr_config { u32 map_tile_count; u32 map_row_offset; #endif - u32 no_of_sm; - struct nvgpu_sm_info *sm_to_cluster; }; #endif /* NVGPU_GR_CONFIG_PRIV_H */ diff --git a/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h b/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h index 72e3a3cd3..f63f49075 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h +++ b/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h @@ -28,100 +28,172 @@ struct nvgpu_ctxsw_ucode_segments; +/** GPCCS boot signature for T18X chip, type: with reserved. */ +#define FALCON_UCODE_SIG_T18X_GPCCS_WITH_RESERVED 0x68edab34U + +/** FECS boot signature for T21X chip, type: with DMEM size. */ +#define FALCON_UCODE_SIG_T21X_FECS_WITH_DMEM_SIZE 0x9121ab5cU +/** FECS boot signature for T21X chip, type: with reserved. */ +#define FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED 0x9125ab5cU +/** FECS boot signature for T21X chip, type: without reserved. */ +#define FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED 0x93671b7dU +/** FECS boot signature for T21X chip, type: without reserved2. */ +#define FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED2 0x4d6cbc10U +/** GPCCS boot signature for T21X chip, type: with reserved. */ +#define FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED 0x3d3d65e2U +/** GPCCS boot signature for T21X chip, type: without reserved. */ +#define FALCON_UCODE_SIG_T21X_GPCCS_WITHOUT_RESERVED 0x393161daU + +/** FECS boot signature for T12X chip, type: with reserved. */ +#define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78U +/** FECS boot signature for T12X chip, type: without reserved. */ +#define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344bU +/** FECS boot signature for T12X chip, type: older. */ +#define FALCON_UCODE_SIG_T12X_FECS_OLDER 0x56da09fU + +/** GPCCS boot signature for T12X chip, type: with reserved. */ +#define FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED 0x303465d5U +/** GPCCS boot signature for T12X chip, type: without reserved. */ +#define FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED 0x3fdd33d3U +/** GPCCS boot signature for T12X chip, type: older. */ +#define FALCON_UCODE_SIG_T12X_GPCCS_OLDER 0x53d7877U + +enum wait_ucode_status { + /** Status of ucode wait operation : LOOP. */ + WAIT_UCODE_LOOP, + /** Status of ucode wait operation : timedout. */ + WAIT_UCODE_TIMEOUT, + /** Status of ucode wait operation : error. */ + WAIT_UCODE_ERROR, + /** Status of ucode wait operation : success. */ + WAIT_UCODE_OK +}; + +/** Falcon operation condition : EQUAL. */ +#define GR_IS_UCODE_OP_EQUAL 0U +/** Falcon operation condition : NOT_EQUAL. */ +#define GR_IS_UCODE_OP_NOT_EQUAL 1U +/** Falcon operation condition : AND. */ +#define GR_IS_UCODE_OP_AND 2U +/** Falcon operation condition : LESSER. */ +#define GR_IS_UCODE_OP_LESSER 3U +/** Falcon operation condition : LESSER_EQUAL. */ +#define GR_IS_UCODE_OP_LESSER_EQUAL 4U +/** Falcon operation condition : SKIP. */ +#define GR_IS_UCODE_OP_SKIP 5U + +/** Mailbox value in case of successful operation. */ +#define FALCON_UCODE_HANDSHAKE_INIT_COMPLETE 1U + +/** + * FECS method operation structure. + * + * This structure defines the protocol for communication with FECS + * microcontroller. + */ struct nvgpu_fecs_method_op { struct { + /** Method address to send to FECS microcontroller. */ u32 addr; + /** Method data to send to FECS microcontroller. */ u32 data; } method; struct { + /** Mailbox ID to perform operation. */ u32 id; + /** Mailbox data to be written. */ u32 data; + /** Mailbox clear value. */ u32 clr; + /** Last read mailbox value. */ u32 *ret; + /** Mailbox value in case of operation success. */ u32 ok; + /** Mailbox value in case of operation failure. */ u32 fail; } mailbox; struct { + /** Operation success condition. */ u32 ok; + /** Operation fail condition. */ u32 fail; } cond; - }; +/** + * CTXSW falcon bootloader descriptor structure. + */ struct nvgpu_ctxsw_bootloader_desc { + /** Start offset, unused. */ u32 start_offset; + /** Size, unused. */ u32 size; + /** IMEM offset. */ u32 imem_offset; + /** Falcon boot vector. */ u32 entry_point; }; +/** + * CTXSW ucode information structure. + */ struct nvgpu_ctxsw_ucode_info { - u64 *p_va; + /** Memory to store ucode instance block. */ struct nvgpu_mem inst_blk_desc; + /** Memory to store ucode contents locally. */ struct nvgpu_mem surface_desc; + /** Ucode segments for FECS. */ struct nvgpu_ctxsw_ucode_segments fecs; + /** Ucode segments for GPCCS. */ struct nvgpu_ctxsw_ucode_segments gpccs; }; +/** + * Structure to store various sizes queried from FECS + */ struct nvgpu_gr_falcon_query_sizes { + /** Size of golden context image. */ u32 golden_image_size; + +#ifdef CONFIG_NVGPU_DEBUGGER u32 pm_ctxsw_image_size; +#endif + +#ifdef CONFIG_NVGPU_GRAPHICS u32 preempt_image_size; u32 zcull_image_size; +#endif }; +/** + * GR falcon data structure. + * + * This structure stores all data required to load and boot CTXSW ucode, + * and also to communicate with FECS microcontroller. + */ struct nvgpu_gr_falcon { + /** + * CTXSW ucode information structure. + */ struct nvgpu_ctxsw_ucode_info ctxsw_ucode_info; - struct nvgpu_mutex fecs_mutex; /* protect fecs method */ + + /** + * Mutex to protect all FECS methods. + */ + struct nvgpu_mutex fecs_mutex; + + /** + * Flag to skip ucode initialization if it is already done. + */ bool skip_ucode_init; + /** + * Structure to hold various sizes that are queried from FECS + * microcontroller. + */ struct nvgpu_gr_falcon_query_sizes sizes; }; -enum wait_ucode_status { - WAIT_UCODE_LOOP, - WAIT_UCODE_TIMEOUT, - WAIT_UCODE_ERROR, - WAIT_UCODE_OK -}; - -#define GR_IS_UCODE_OP_EQUAL 0U -#define GR_IS_UCODE_OP_NOT_EQUAL 1U -#define GR_IS_UCODE_OP_AND 2U -#define GR_IS_UCODE_OP_LESSER 3U -#define GR_IS_UCODE_OP_LESSER_EQUAL 4U -#define GR_IS_UCODE_OP_SKIP 5U - -enum { - eUcodeHandshakeInitComplete = 1, - eUcodeHandshakeMethodFinished -}; - -/* sums over the ucode files as sequences of u32, computed to the - * boot_signature field in the structure above */ - -/* T18X FECS remains same as T21X, - * so FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED used - * for T18X*/ -#define FALCON_UCODE_SIG_T18X_GPCCS_WITH_RESERVED 0x68edab34U -#define FALCON_UCODE_SIG_T21X_FECS_WITH_DMEM_SIZE 0x9121ab5cU -#define FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED 0x9125ab5cU -#define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78U -#define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344bU -#define FALCON_UCODE_SIG_T12X_FECS_OLDER 0x56da09fU - -#define FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED 0x3d3d65e2U -#define FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED 0x303465d5U -#define FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED 0x3fdd33d3U -#define FALCON_UCODE_SIG_T12X_GPCCS_OLDER 0x53d7877U - -#define FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED 0x93671b7dU -#define FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED2 0x4d6cbc10U - -#define FALCON_UCODE_SIG_T21X_GPCCS_WITHOUT_RESERVED 0x393161daU - - #endif /* GR_FALCON_PRIV_H */ - diff --git a/drivers/gpu/nvgpu/common/gr/gr_intr_priv.h b/drivers/gpu/nvgpu/common/gr/gr_intr_priv.h index 9abc2c2d2..c75a987c7 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_intr_priv.h +++ b/drivers/gpu/nvgpu/common/gr/gr_intr_priv.h @@ -28,49 +28,174 @@ struct nvgpu_channel; +/** + * Size of lookup buffer used for context translation to GPU channel + * and TSG identifiers. + * This value must be a power of 2. + */ +#define GR_CHANNEL_MAP_TLB_SIZE 2U + +/** + * GR interrupt information struct. + * + * This structure maintains information on pending GR engine interrupts. + */ struct nvgpu_gr_intr_info { + /** + * This value is set in case notification interrupt is pending. + * Same value is used to clear the interrupt. + */ u32 notify; + /** + * This value is set in case semaphore interrupt is pending. + * Same value is used to clear the interrupt. + */ u32 semaphore; + /** + * This value is set in case illegal notify interrupt is pending. + * Same value is used to clear the interrupt. + */ u32 illegal_notify; + /** + * This value is set in case illegal method interrupt is pending. + * Same value is used to clear the interrupt. + */ u32 illegal_method; + /** + * This value is set in case illegal class interrupt is pending. + * Same value is used to clear the interrupt. + */ u32 illegal_class; + /** + * This value is set in case FECS error interrupt is pending. + * Same value is used to clear the interrupt. + */ u32 fecs_error; + /** + * This value is set in case illegal class interrupt is pending. + * Same value is used to clear the interrupt. + */ u32 class_error; + /** + * This value is set in case firmware method interrupt is pending. + * Same value is used to clear the interrupt. + */ u32 fw_method; + /** + * This value is set in case exception is pending in graphics pipe. + * Same value is used to clear the interrupt. + */ u32 exception; }; +/** + * TPC exception data structure. + * + * TPC exceptions can be decomposed into exceptions triggered by its + * subunits. This structure keeps track of which subunits have + * triggered exception. + */ struct nvgpu_gr_tpc_exception { + /** + * This flag is set in case TEX exception is pending. + */ bool tex_exception; + /** + * This flag is set in case SM exception is pending. + */ bool sm_exception; + /** + * This flag is set in case MPC exception is pending. + */ bool mpc_exception; + /** + * This flag is set in case PE exception is pending. + */ bool pe_exception; }; +/** + * GR ISR data structure. + * + * This structure holds all necessary information to handle all GR engine + * error/exception interrupts. + */ struct nvgpu_gr_isr_data { + /** + * Contents of TRAPPED_ADDR register used to decode below + * fields. + */ u32 addr; + /** + * Low word of the trapped method data. + */ u32 data_lo; + /** + * High word of the trapped method data. + */ u32 data_hi; + /** + * Information of current context. + */ u32 curr_ctx; + /** + * Pointer to faulted GPU channel. + */ struct nvgpu_channel *ch; + /** + * Address of the trapped method. + */ u32 offset; + /** + * Subchannel ID of the trapped method. + */ u32 sub_chan; + /** + * Class ID corresponding to above subchannel. + */ u32 class_num; }; +/** + * Details of lookup buffer used to translate context to GPU + * channel/TSG identifiers. + */ struct gr_channel_map_tlb_entry { + /** + * Information of context. + */ u32 curr_ctx; + /** + * GPU channel ID. + */ u32 chid; + /** + * GPU Time Slice Group ID. + */ u32 tsgid; }; +/** + * GR interrupt management data structure. + * + * This structure holds various fields to manage GR engine interrupt + * handling. + */ struct nvgpu_gr_intr { - -#define GR_CHANNEL_MAP_TLB_SIZE 2U /* must of power of 2 */ + /** + * Lookup buffer structure used to translate context to GPU + * channel and TSG identifiers. + */ struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; + /** + * Entry in lookup buffer that should be overwritten if there is + * no remaining free entry. + */ u32 channel_tlb_flush_index; + /** + * Spinlock for all lookup buffer accesses. + */ struct nvgpu_spinlock ch_tlb_lock; - }; #endif /* NVGPU_GR_INTR_PRIV_H */ diff --git a/drivers/gpu/nvgpu/common/gr/gr_priv.h b/drivers/gpu/nvgpu/common/gr/gr_priv.h index 3090f47ad..0ccfb61e9 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_priv.h +++ b/drivers/gpu/nvgpu/common/gr/gr_priv.h @@ -34,23 +34,77 @@ struct nvgpu_gr_config; struct nvgpu_gr_zbc; struct nvgpu_gr_zcull; #endif +#ifdef CONFIG_NVGPU_DEBUGGER struct nvgpu_gr_hwpm_map; -struct gk20a_cs_snapshot; +#endif +/** + * GR engine data structure. + * + * This is the parent structure to all other GR engine data structures, + * and holds a pointer to all of them. This structure also stores + * various fields to track GR engine initialization state. + * + * Pointer to this structure is maintained in GPU driver structure. + */ struct nvgpu_gr { + /** + * Pointer to GPU driver struct. + */ struct gk20a *g; + /** + * Condition variable for GR initialization. + * Waiters shall wait on this condition to ensure GR engine + * is initialized. + */ struct nvgpu_cond init_wq; + + /** + * Flag to indicate if GR engine is initialized. + */ bool initialized; + /** + * Pointer to global context buffer descriptor structure. + */ struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer; + /** + * Pointer to Golden context image structure. + */ struct nvgpu_gr_obj_ctx_golden_image *golden_image; + /** + * Pointer to GR context descriptor structure. + */ struct nvgpu_gr_ctx_desc *gr_ctx_desc; + /** + * Pointer to GR configuration structure. + */ struct nvgpu_gr_config *config; + /** + * Pointer to GR falcon data structure. + */ + struct nvgpu_gr_falcon *falcon; + + /** + * Pointer to GR interrupt data structure. + */ + struct nvgpu_gr_intr *intr; + + /** + * Function pointer to remove GR s/w support. + */ + void (*remove_support)(struct gk20a *g); + + /** + * Flag to indicate GR s/w has been initialized. + */ + bool sw_ready; + #ifdef CONFIG_NVGPU_DEBUGGER struct nvgpu_gr_hwpm_map *hwpm_map; #endif @@ -61,13 +115,6 @@ struct nvgpu_gr { struct nvgpu_gr_zbc *zbc; #endif - struct nvgpu_gr_falcon *falcon; - - struct nvgpu_gr_intr *intr; - - void (*remove_support)(struct gk20a *g); - bool sw_ready; - #ifdef CONFIG_NVGPU_NON_FUSA u32 fecs_feature_override_ecc_val; #endif @@ -76,8 +123,10 @@ struct nvgpu_gr { u32 cilp_preempt_pending_chid; #endif +#if defined(CONFIG_NVGPU_RECOVERY) || defined(CONFIG_NVGPU_DEBUGGER) struct nvgpu_mutex ctxsw_disable_mutex; int ctxsw_disable_count; +#endif }; #endif /* NVGPU_GR_PRIV_H */ diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c index 25fb64d68..eafa96cf9 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c @@ -577,7 +577,7 @@ int gm20b_gr_falcon_wait_ctxsw_ready(struct gk20a *g) ret = gm20b_gr_falcon_ctx_wait_ucode(g, 0, NULL, GR_IS_UCODE_OP_EQUAL, - eUcodeHandshakeInitComplete, + FALCON_UCODE_HANDSHAKE_INIT_COMPLETE, GR_IS_UCODE_OP_SKIP, 0, false); if (ret != 0) { nvgpu_err(g, "falcon ucode init timeout");