From cb1c2b7845db743798bb615dc1c6dd1a797cdb74 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Mon, 10 Dec 2018 14:37:38 +0530 Subject: [PATCH] gpu: nvgpu: update MINION falcon base addr init Prepare new hal api g->ops.nvlink.falcon_base_addr to get the MINION falcon base address. JIRA NVGPU-1587 Change-Id: I83a38bf78fd582ea715248900587c1e8e209da3c Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/1969433 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/falcon/falcon_gv100.c | 2 +- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 5 +++++ drivers/gpu/nvgpu/gv100/nvlink_gv100.h | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 + drivers/gpu/nvgpu/tu104/hal_tu104.c | 1 + 6 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_gv100.c b/drivers/gpu/nvgpu/common/falcon/falcon_gv100.c index 2f5feb584..801a08975 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_gv100.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_gv100.c @@ -59,7 +59,7 @@ int gv100_falcon_hal_sw_init(struct nvgpu_falcon *flcn) switch (flcn->flcn_id) { case FALCON_ID_MINION: - flcn->flcn_base = g->nvlink.minion_base; + flcn->flcn_base = g->ops.nvlink.falcon_base_addr(g); flcn->is_falcon_supported = true; flcn->is_interrupt_enabled = true; break; diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index f2e7128a3..8cb5b35cf 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -1048,6 +1048,7 @@ static const struct gpu_ops gv100_ops = { }, #if defined(CONFIG_TEGRA_NVLINK) .nvlink = { + .falcon_base_addr = gv100_nvlink_falcon_base_addr, .discover_ioctrl = gv100_nvlink_discover_ioctrl, .discover_link = gv100_nvlink_discover_link, .init = gv100_nvlink_init, diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index ec8a23cea..0a94c6f42 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c @@ -2773,4 +2773,9 @@ int gv100_nvlink_speed_config(struct gk20a *g) g->nvlink.initpll_cmd = minion_nvlink_dl_cmd_command_initpll_1_v(); return 0; } + +u32 gv100_nvlink_falcon_base_addr(struct gk20a *g) +{ + return g->nvlink.minion_base; +} #endif /* CONFIG_TEGRA_NVLINK */ diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.h b/drivers/gpu/nvgpu/gv100/nvlink_gv100.h index 7150aba32..34d34f082 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.h +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.h @@ -55,4 +55,5 @@ int gv100_nvlink_reg_init(struct gk20a *g); int gv100_nvlink_shutdown(struct gk20a *g); int gv100_nvlink_early_init(struct gk20a *g); int gv100_nvlink_speed_config(struct gk20a *g); +u32 gv100_nvlink_falcon_base_addr(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 25eb66db3..4b3dac339 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1438,6 +1438,7 @@ struct gpu_ops { int (*read_gcplex_config_fuse)(struct gk20a *g, u32 *val); } fuse; struct { + u32 (*falcon_base_addr)(struct gk20a *g); int (*init)(struct gk20a *g); int (*discover_ioctrl)(struct gk20a *g); int (*discover_link)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 98a553d86..91726136d 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -1080,6 +1080,7 @@ static const struct gpu_ops tu104_ops = { }, #if defined(CONFIG_TEGRA_NVLINK) .nvlink = { + .falcon_base_addr = gv100_nvlink_falcon_base_addr, .discover_ioctrl = gv100_nvlink_discover_ioctrl, .discover_link = gv100_nvlink_discover_link, .init = gv100_nvlink_init,