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gpu: nvgpu: Fix LibC MISRA 17.7 in common
MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for all 17.7 violations instandard C functions in common code. JIRA NVGPU-1036 Change-Id: Id6dea92df371e71b22b54cd7a521fc22812f9b69 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929899 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -84,10 +84,10 @@ static void sec2_seq_init(struct nvgpu_sec2 *sec2)
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nvgpu_log_fn(sec2->g, " ");
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memset(sec2->seq, 0,
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(void) memset(sec2->seq, 0,
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sizeof(struct sec2_sequence) * SEC2_MAX_NUM_SEQUENCES);
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memset(sec2->sec2_seq_tbl, 0, sizeof(sec2->sec2_seq_tbl));
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(void) memset(sec2->sec2_seq_tbl, 0, sizeof(sec2->sec2_seq_tbl));
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for (i = 0; i < SEC2_MAX_NUM_SEQUENCES; i++) {
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sec2->seq[i].id = (u8)i;
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@@ -218,7 +218,7 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
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nvgpu_log_fn(g, " ");
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/* send message to load falcon */
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memset(&cmd, 0, sizeof(struct nv_flcn_cmd_sec2));
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(void) memset(&cmd, 0, sizeof(struct nv_flcn_cmd_sec2));
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cmd.hdr.unit_id = NV_SEC2_UNIT_ACR;
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cmd.hdr.size = PMU_CMD_HDR_SIZE +
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sizeof(struct nv_sec2_acr_cmd_bootstrap_falcon);
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