From cb4a27fb0f7f3c3aebd500340b9f266e1654e91b Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Mon, 8 Jul 2019 14:51:15 +0530 Subject: [PATCH] gpu: nvgpu: compile out xve hal from safety build xve functions are available only with DGPU hence compile them based on CONFIG_NVGPU_DGPU. JIRA NVGPU-3657 Change-Id: I4123043518935dd93e2104644d6f706fe7243f7f Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2149496 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile.sources | 6 +++--- drivers/gpu/nvgpu/common/init/nvgpu_init.c | 4 ++++ drivers/gpu/nvgpu/hal/xve/xve_gp106.h | 3 +++ drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 ++ 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 84e1bee2d..b0ff7566f 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -212,8 +212,7 @@ srcs += common/utils/enabled.c \ hal/pmu/pmu_gp106.c \ hal/pmu/pmu_gv11b.c \ hal/top/top_gm20b.c \ - hal/top/top_gp106.c \ - hal/xve/xve_gp106.c + hal/top/top_gp106.c # Source files below are functionaly safe (FuSa) and must always be included. srcs += hal/mm/mm_gv11b_fusa.c \ @@ -617,7 +616,8 @@ srcs += common/sec2/sec2.c \ hal/pramin/pramin_init.c \ hal/pramin/pramin_tu104.c \ hal/bios/bios_tu104.c \ - hal/top/top_gv100.c + hal/top/top_gv100.c \ + hal/xve/xve_gp106.c ifeq ($(CONFIG_NVGPU_COMPRESSION),1) srcs += hal/cbc/cbc_tu104.c diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 465843606..cb8bbd30e 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -179,6 +179,7 @@ int gk20a_finalize_poweron(struct gk20a *g) g->power_on = true; +#ifdef CONFIG_NVGPU_DGPU /* * Before probing the GPU make sure the GPU's state is cleared. This is * relevant for rebind operations. @@ -187,6 +188,7 @@ int gk20a_finalize_poweron(struct gk20a *g) g->ops.xve.reset_gpu(g); g->gpu_reset_done = true; } +#endif /* * Do this early so any early VMs that get made are capable of mapping @@ -494,6 +496,7 @@ int gk20a_finalize_poweron(struct gk20a *g) } #endif +#ifdef CONFIG_NVGPU_DGPU if (g->ops.xve.available_speeds != NULL) { u32 speed; @@ -512,6 +515,7 @@ int gk20a_finalize_poweron(struct gk20a *g) goto done; } } +#endif #if defined(CONFIG_TEGRA_GK20A_NVHOST) if (nvgpu_has_syncpoints(g) && (g->syncpt_unit_size != 0UL)) { diff --git a/drivers/gpu/nvgpu/hal/xve/xve_gp106.h b/drivers/gpu/nvgpu/hal/xve/xve_gp106.h index bb758873c..48da02449 100644 --- a/drivers/gpu/nvgpu/hal/xve/xve_gp106.h +++ b/drivers/gpu/nvgpu/hal/xve/xve_gp106.h @@ -23,6 +23,8 @@ #ifndef NVGPU_XVE_GP106_H #define NVGPU_XVE_GP106_H +#ifdef CONFIG_NVGPU_DGPU + #include #include #include @@ -66,4 +68,5 @@ void xve_rearm_msi_gp106(struct gk20a *g); void xve_enable_shadow_rom_gp106(struct gk20a *g); void xve_disable_shadow_rom_gp106(struct gk20a *g); +#endif #endif /* NVGPU_XVE_GP106_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index a9d68a5b6..57fc31e9d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1664,6 +1664,7 @@ struct gpu_ops { u32 (*get_max_buffer_size)(struct gk20a *g); } css; #endif +#ifdef CONFIG_NVGPU_DGPU struct { int (*get_speed)(struct gk20a *g, u32 *xve_link_speed); int (*set_speed)(struct gk20a *g, u32 xve_link_speed); @@ -1679,6 +1680,7 @@ struct gpu_ops { void (*disable_shadow_rom)(struct gk20a *g); u32 (*get_link_control_status)(struct gk20a *g); } xve; +#endif struct { void (*reset)(struct nvgpu_falcon *flcn); void (*set_irq)(struct nvgpu_falcon *flcn, bool enable,