diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index b3c451bf2..5ffdf0763 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -52,6 +52,7 @@ ccflags-y += -DCONFIG_NVGPU_IOCTL_NON_FUSA
 ccflags-y += -DCONFIG_NVGPU_NON_FUSA
 ccflags-y += -DCONFIG_NVGPU_INJECT_HWERR
 ccflags-y += -DCONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
+ccflags-y += -DCONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 ccflags-y += -DCONFIG_NVGPU_SW_SEMAPHORE
 ccflags-y += -DCONFIG_NVGPU_FENCE
 
diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs
index 679c177dc..10fb6d806 100644
--- a/drivers/gpu/nvgpu/Makefile.shared.configs
+++ b/drivers/gpu/nvgpu/Makefile.shared.configs
@@ -185,6 +185,9 @@ NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_IOCTL_NON_FUSA
 CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT := 1
 NVGPU_COMMON_CFLAGS                    += -DCONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
 
+CONFIG_NVGPU_SET_FALCON_ACCESS_MAP := 1
+NVGPU_COMMON_CFLAGS                += -DCONFIG_NVGPU_SET_FALCON_ACCESS_MAP
+
 # Enable SW Semaphore for normal build
 CONFIG_NVGPU_SW_SEMAPHORE       := 1
 NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_SW_SEMAPHORE
diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c
index ba9b29f8c..038aa73b8 100644
--- a/drivers/gpu/nvgpu/common/gr/gr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr.c
@@ -299,9 +299,11 @@ static int gr_init_access_map(struct gk20a *g, struct nvgpu_gr *gr)
 	u32 nr_pages =
 		DIV_ROUND_UP(NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP_SIZE,
 			     PAGE_SIZE);
+	u32 nr_pages_size = nvgpu_safe_mult_u32(PAGE_SIZE, nr_pages);
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 	u32 *whitelist = NULL;
 	u32 w, num_entries = 0U;
-	u32 nr_pages_size = nvgpu_safe_mult_u32(PAGE_SIZE, nr_pages);
+#endif
 
 	mem = nvgpu_gr_global_ctx_buffer_get_mem(gr->global_ctx_buffer,
 			NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP);
@@ -311,6 +313,7 @@ static int gr_init_access_map(struct gk20a *g, struct nvgpu_gr *gr)
 
 	nvgpu_memset(g, mem, 0, 0, nr_pages_size);
 
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 	g->ops.gr.init.get_access_map(g, &whitelist, &num_entries);
 
 	for (w = 0U; w < num_entries; w++) {
@@ -326,6 +329,7 @@ static int gr_init_access_map(struct gk20a *g, struct nvgpu_gr *gr)
 			  + map_shift);
 		nvgpu_mem_wr32(g, mem, (u64)map_byte / (u64)sizeof(u32), x);
 	}
+#endif
 
 	return 0;
 }
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
index db1790f32..323d8b54e 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
@@ -77,6 +77,7 @@ void gm20b_gr_init_gpc_mmu(struct gk20a *g)
 			nvgpu_ltc_get_ltc_count(g));
 }
 
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 void gm20b_gr_init_get_access_map(struct gk20a *g,
 				   u32 **whitelist, u32 *num_entries)
 {
@@ -119,6 +120,7 @@ void gm20b_gr_init_get_access_map(struct gk20a *g,
 	array_size = ARRAY_SIZE(wl_addr_gm20b);
 	*num_entries = nvgpu_safe_cast_u64_to_u32(array_size);
 }
+#endif
 
 void gm20b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid,
 				   struct nvgpu_gr_config *gr_config)
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h
index bf68f7477..81b049c65 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h
@@ -69,8 +69,10 @@ u32 gm20b_gr_init_get_patch_slots(struct gk20a *g,
 
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 void gm20b_gr_init_gpc_mmu(struct gk20a *g);
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 void gm20b_gr_init_get_access_map(struct gk20a *g,
 				   u32 **whitelist, u32 *num_entries);
+#endif
 void gm20b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid,
 				   struct nvgpu_gr_config *gr_config);
 u32 gm20b_gr_init_get_sm_id_size(void);
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
index 0ca21b33e..ad540955b 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
@@ -37,6 +37,7 @@
 
 #define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000U
 
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 void gp10b_gr_init_get_access_map(struct gk20a *g,
 				   u32 **whitelist, u32 *num_entries)
 {
@@ -79,6 +80,7 @@ void gp10b_gr_init_get_access_map(struct gk20a *g,
 	array_size = ARRAY_SIZE(wl_addr_gp10b);
 	*num_entries = nvgpu_safe_cast_u64_to_u32(array_size);
 }
+#endif
 
 int gp10b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
 			       struct nvgpu_gr_config *gr_config)
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h
index 163375f8f..b14f34171 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h
@@ -51,8 +51,10 @@ void gp10b_gr_init_get_default_preemption_modes(
 	u32 *default_graphics_preempt_mode, u32 *default_compute_preempt_mode);
 
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 void gp10b_gr_init_get_access_map(struct gk20a *g,
 				   u32 **whitelist, u32 *num_entries);
+#endif
 int gp10b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
 			       struct nvgpu_gr_config *gr_config);
 int gp10b_gr_init_fs_state(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h
index 62beeb1a1..33e424f64 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h
@@ -35,8 +35,10 @@ u32 gv11b_gr_init_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc,
 void gv11b_gr_init_ecc_scrub_reg(struct gk20a *g,
 				 struct nvgpu_gr_config *gr_config);
 void gv11b_gr_init_gpc_mmu(struct gk20a *g);
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 void gv11b_gr_init_get_access_map(struct gk20a *g,
 				   u32 **whitelist, u32 *num_entries);
+#endif
 void gv11b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid,
 				   struct nvgpu_gr_config *gr_config);
 int gv11b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
index ff18a4f72..e6deb3ef3 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
@@ -340,6 +340,7 @@ void gv11b_gr_init_gpc_mmu(struct gk20a *g)
 			g->ops.fb.mmu_debug_rd(g));
 }
 
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 void gv11b_gr_init_get_access_map(struct gk20a *g,
 				   u32 **whitelist, u32 *num_entries)
 {
@@ -382,6 +383,7 @@ void gv11b_gr_init_get_access_map(struct gk20a *g,
 	array_size = ARRAY_SIZE(wl_addr_gv11b);
 	*num_entries = nvgpu_safe_cast_u64_to_u32(array_size);
 }
+#endif
 
 void gv11b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid,
 				   struct nvgpu_gr_config *gr_config)
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
index 595031f14..bd027e776 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
@@ -373,7 +373,9 @@ static const struct gpu_ops gm20b_ops = {
 			.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,
 			.gpc_mmu = gm20b_gr_init_gpc_mmu,
 			.fifo_access = gm20b_gr_init_fifo_access,
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 			.get_access_map = gm20b_gr_init_get_access_map,
+#endif
 			.get_sm_id_size = gm20b_gr_init_get_sm_id_size,
 			.sm_id_config = gm20b_gr_init_sm_id_config,
 			.sm_id_numbering = gm20b_gr_init_sm_id_numbering,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
index 5ad2b2e83..a9e4b2bca 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
@@ -427,7 +427,9 @@ static const struct gpu_ops gp10b_ops = {
 			.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,
 			.gpc_mmu = gm20b_gr_init_gpc_mmu,
 			.fifo_access = gm20b_gr_init_fifo_access,
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 			.get_access_map = gp10b_gr_init_get_access_map,
+#endif
 			.get_sm_id_size = gp10b_gr_init_get_sm_id_size,
 			.sm_id_config = gp10b_gr_init_sm_id_config,
 			.sm_id_numbering = gm20b_gr_init_sm_id_numbering,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index 5d421f67d..6d67cd908 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -514,7 +514,9 @@ static const struct gpu_ops gv11b_ops = {
 			.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,
 			.gpc_mmu = gv11b_gr_init_gpc_mmu,
 			.fifo_access = gm20b_gr_init_fifo_access,
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 			.get_access_map = gv11b_gr_init_get_access_map,
+#endif
 			.get_sm_id_size = gp10b_gr_init_get_sm_id_size,
 			.sm_id_config = gv11b_gr_init_sm_id_config,
 			.sm_id_numbering = gv11b_gr_init_sm_id_numbering,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index d7c6d01c0..fd40c006b 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -543,7 +543,9 @@ static const struct gpu_ops tu104_ops = {
 			.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,
 			.gpc_mmu = gv11b_gr_init_gpc_mmu,
 			.fifo_access = gm20b_gr_init_fifo_access,
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 			.get_access_map = gv11b_gr_init_get_access_map,
+#endif
 			.get_sm_id_size = gp10b_gr_init_get_sm_id_size,
 			.sm_id_config = gv11b_gr_init_sm_id_config,
 			.sm_id_numbering = gv11b_gr_init_sm_id_numbering,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 4b7207423..10233ef2e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -745,8 +745,10 @@ struct gpu_ops {
 			void (*pes_vsc_stream)(struct gk20a *g);
 			void (*gpc_mmu)(struct gk20a *g);
 			void (*fifo_access)(struct gk20a *g, bool enable);
+#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 			void (*get_access_map)(struct gk20a *g,
 				      u32 **whitelist, u32 *num_entries);
+#endif
 			u32 (*get_sm_id_size)(void);
 			int (*sm_id_config)(struct gk20a *g, u32 *tpc_sm_id,
 					    struct nvgpu_gr_config *gr_config);