diff --git a/drivers/gpu/nvgpu/hal/clk/clk_gm20b.c b/drivers/gpu/nvgpu/hal/clk/clk_gm20b.c index dfe157fa8..711987834 100644 --- a/drivers/gpu/nvgpu/hal/clk/clk_gm20b.c +++ b/drivers/gpu/nvgpu/hal/clk/clk_gm20b.c @@ -381,15 +381,20 @@ static void clk_config_dvfs_ndiv(int mv, u32 n_eff, struct na_dvfs *d) } /* Voltage dependent configuration */ -static void clk_config_dvfs(struct gk20a *g, struct pll *gpll) +static int clk_config_dvfs(struct gk20a *g, struct pll *gpll) { struct na_dvfs *d = &gpll->dvfs; d->mv = g->ops.clk.predict_mv_at_hz_cur_tfloor(&g->clk, rate_gpc2clk_to_gpu(gpll->freq)); + if (d->mv < 0) { + return d->mv; + } clk_config_dvfs_detection(d->mv, d); clk_config_dvfs_ndiv(d->mv, gpll->N, d); + + return 0; } /* Update DVFS detection settings in flight */ @@ -1047,7 +1052,10 @@ static int clk_program_na_gpc_pll(struct gk20a *g, struct pll *gpll_new, struct pll *gpll_old = &g->clk.gpc_pll_last; BUG_ON(gpll_new->M != 1U); /* the only MDIV in NA mode */ - clk_config_dvfs(g, gpll_new); + ret = clk_config_dvfs(g, gpll_new); + if (ret < 0) { + return ret; + } /* * In cases below no intermediate steps in PLL DVFS configuration are diff --git a/drivers/gpu/nvgpu/os/linux/clk.c b/drivers/gpu/nvgpu/os/linux/clk.c index 77c5e0f61..4347e6c22 100644 --- a/drivers/gpu/nvgpu/os/linux/clk.c +++ b/drivers/gpu/nvgpu/os/linux/clk.c @@ -18,8 +18,14 @@ #include +#ifdef CONFIG_TEGRA_DVFS #include +#endif /* CONFIG_TEGRA_DVFS */ + +#ifdef CONFIG_NV_TEGRA_BPMP #include +#endif /* CONFIG_NV_TEGRA_BPMP */ + #include #include "clk.h" @@ -85,6 +91,7 @@ static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g) { struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g)); +#ifdef CONFIG_TEGRA_DVFS /* * On Tegra platforms with GPCPLL bus (gbus) GPU tegra_clk clock exposed * to frequency governor is a shared user on the gbus. The latter can be @@ -93,10 +100,14 @@ static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g) if (g->clk.tegra_clk) return tegra_dvfs_get_fmax_at_vmin_safe_t( g->clk.tegra_clk_parent); +#endif - if (platform->maxmin_clk_id) + if (platform->maxmin_clk_id) { +#ifdef CONFIG_NV_TEGRA_BPMP return tegra_bpmp_dvfs_get_fmax_at_vmin( platform->maxmin_clk_id); +#endif + } return 0; } @@ -117,8 +128,12 @@ static u32 nvgpu_linux_get_ref_clock_rate(struct gk20a *g) static int nvgpu_linux_predict_mv_at_hz_cur_tfloor(struct clk_gk20a *clk, unsigned long rate) { +#ifdef CONFIG_TEGRA_DVFS return tegra_dvfs_predict_mv_at_hz_cur_tfloor( clk->tegra_clk_parent, rate); +#else + return -EINVAL; +#endif } static unsigned long nvgpu_linux_get_maxrate(struct gk20a *g, u32 api_domain) @@ -128,7 +143,11 @@ static unsigned long nvgpu_linux_get_maxrate(struct gk20a *g, u32 api_domain) switch (api_domain) { case CTRL_CLK_DOMAIN_GPCCLK: +#ifdef CONFIG_TEGRA_DVFS ret = tegra_dvfs_get_maxrate(g->clk.tegra_clk_parent); +#else + ret = 0; +#endif /* If dvfs not supported */ if (ret == 0) { int err = nvgpu_clk_arb_get_arbiter_clk_range(g, diff --git a/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c index d429f6a1e..dfc933b97 100644 --- a/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c @@ -28,9 +28,11 @@ #include #include #include -#if defined(CONFIG_COMMON_CLK) + +#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_TEGRA_DVFS) #include -#endif +#endif /* CONFIG_COMMON_CLK && CONFIG_TEGRA_DVFS */ + #ifdef CONFIG_TEGRA_BWMGR #include #endif @@ -173,8 +175,12 @@ static unsigned long gk20a_tegra_get_emc_rate(struct gk20a *g, unsigned long emc_rate, emc_scale; gpu_freq = clk_get_rate(g->clk.tegra_clk); +#ifdef CONFIG_TEGRA_DVFS gpu_fmax_at_vmin = tegra_dvfs_get_fmax_at_vmin_safe_t( clk_get_parent(g->clk.tegra_clk)); +#else + gpu_fmax_at_vmin = 0; +#endif /* When scaling emc, account for the gpu load when the * gpu frequency is less than or equal to fmax@vmin. */ @@ -296,8 +302,10 @@ static bool gk20a_tegra_is_railgated(struct device *dev) struct gk20a_platform *platform = dev_get_drvdata(dev); bool ret = false; +#ifdef CONFIG_TEGRA_DVFS if (!nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) ret = !tegra_dvfs_is_rail_up(platform->gpu_rail); +#endif return ret; } @@ -314,9 +322,11 @@ static int gm20b_tegra_railgate(struct device *dev) struct gk20a_platform *platform = dev_get_drvdata(dev); int ret = 0; +#ifdef CONFIG_TEGRA_DVFS if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL) || !tegra_dvfs_is_rail_up(platform->gpu_rail)) return 0; +#endif tegra_mc_flush(MC_CLIENT_GPU); @@ -346,12 +356,14 @@ static int gm20b_tegra_railgate(struct device *dev) tegra_soctherm_gpu_tsens_invalidate(1); +#ifdef CONFIG_TEGRA_DVFS if (tegra_dvfs_is_rail_up(platform->gpu_rail)) { ret = tegra_dvfs_rail_power_down(platform->gpu_rail); if (ret) goto err_power_off; } else pr_info("No GPU regulator?\n"); +#endif #ifdef CONFIG_TEGRA_BWMGR gm20b_bwmgr_set_rate(platform, false); @@ -453,7 +465,9 @@ static int gm20b_tegra_unrailgate(struct device *dev) return 0; err_clk_on: +#ifdef CONFIG_TEGRA_DVFS tegra_dvfs_rail_power_down(platform->gpu_rail); +#endif return ret; } @@ -783,7 +797,7 @@ static int gk20a_tegra_probe(struct device *dev) int ret; struct gk20a *g = platform->g; -#ifdef CONFIG_COMMON_CLK +#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_TEGRA_DVFS) /* DVFS is not guaranteed to be initialized at the time of probe on * kernels with Common Clock Framework enabled. */ @@ -901,8 +915,12 @@ static int gk20a_clk_get_freqs(struct device *dev, if (!gk20a_clk_get(g)) return -ENOSYS; +#ifdef CONFIG_TEGRA_DVFS return tegra_dvfs_get_freqs(clk_get_parent(g->clk.tegra_clk), freqs, num_freqs); +#else + return -EINVAL; +#endif } #endif diff --git a/drivers/gpu/nvgpu/os/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gp10b_tegra.c index 9d362a5bc..b0432db88 100644 --- a/drivers/gpu/nvgpu/os/linux/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/os/linux/platform_gp10b_tegra.c @@ -106,12 +106,14 @@ int gp10b_tegra_get_clocks(struct device *dev) } platform->num_clks = i; +#ifdef CONFIG_NV_TEGRA_BPMP if (platform->clk[0]) { i = tegra_bpmp_dvfs_get_clk_id(dev->of_node, tegra_gp10b_clocks[0].name); if (i > 0) platform->maxmin_clk_id = i; } +#endif return 0; }